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From: Catalin Marinas <catalin.marinas@arm.com>
To: Yann Sionneau <ysionneau@kalrayinc.com>
Cc: Wolfram Sang <wsa@kernel.org>,
	Jan Bottorff <janb@os.amperecomputing.com>,
	Serge Semin <fancer.lancer@gmail.com>,
	Yann Sionneau <yann@sionneau.net>, Will Deacon <will@kernel.org>,
	Jarkko Nikula <jarkko.nikula@linux.intel.com>,
	Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
	Mika Westerberg <mika.westerberg@linux.intel.com>,
	Jan Dabros <jsd@semihalf.com>, Andi Shyti <andi.shyti@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] i2c: designware: Fix corrupted memory seen in the ISR
Date: Tue, 19 Sep 2023 15:51:00 +0100	[thread overview]
Message-ID: <ZQm1UyZ0g7KxRW3a@arm.com> (raw)
In-Reply-To: <da400d3e-a357-1ae8-cb92-728cc4974b67@kalrayinc.com>

On Tue, Sep 19, 2023 at 02:38:22PM +0200, Yann Sionneau wrote:
> Hi,
> 
> On 9/19/23 12:19, Wolfram Sang wrote:
> > > I also agree that a wmb() in the i2c driver is not the more elegant fix.
> > > For similar reasons, we hid barriers in the write*() macros, drivers
> > > need to stay architecture-agnostic as much as possible.
> > Exactly my thinking. I wanted to read this patch discussion later this
> > week. But from glimpsing at it so far, I already wondered why there
> > isn't a memory barrier in the final accessor to the register.
> 
> The regmap accessors used by the designware driver end up calling
> writel_relaxed() and readl_relaxed() : https://elixir.bootlin.com/linux/v6.6-rc2/source/drivers/i2c/busses/i2c-designware-common.c#L71

OK, since it ends up with the *_relaxed() accessors, there are no
barriers here. I wonder whether the regmap API should have both standard
and relaxed variants. If a regmap driver does not populate the
.reg_write_relaxed etc. members, a regmap_write_relaxed() would just
fall back to regmap_write().

We went through similar discussions many years ago around the I/O
accessors and decided to add the barriers to readl/writel() even if they
become more expensive, correctness should be first. The relaxed variants
were added as optimisations if specific memory ordering was not
required. I think the regmap API should follow the same semantics, go
for correctness first as you can't tell what the side-effect of a
regmap_write() is (e.g. kicking off DMA or causing an interrupt on
another CPU).

> In those cases I would say the smp_* barriers are what we are supposed to
> use, isn't it?

While smp_* is ok, it really depends on what the regmap_write() does. Is
it a write to a shared peripheral (if not, you may need a DSB)? Does the
regmap_write() caller know this? That's why I think having the barrier
in dw_reg_write() is better.

If you do want to stick to a fix in i2c_dw_xfer_init(), you could go for
dma_wmb(). While this is not strictly DMA, it's sharing data with
another coherent agent (a different CPU in this instance). The smp_wmb()
is more about communication via memory not involving I/O. But this still
assumes that the caller knows regmap_write() ends up with an I/O
write*() (potentially relaxed).

-- 
Catalin

  reply	other threads:[~2023-09-19 14:51 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-13 23:29 [PATCH v2] i2c: designware: Fix corrupted memory seen in the ISR Jan Bottorff
2023-09-14 18:46 ` Andy Shevchenko
2023-09-14 18:47   ` Andy Shevchenko
2023-09-14 20:52     ` Jan Bottorff
2023-09-15 12:44 ` Jarkko Nikula
2023-09-15 15:21 ` Serge Semin
2023-09-16  1:47   ` Jan Bottorff
2023-09-17  0:01     ` Serge Semin
2023-09-17 20:08       ` Yann Sionneau
2023-09-18 23:14         ` Serge Semin
2023-09-19  3:45           ` Jan Bottorff
2023-09-19  9:55             ` Catalin Marinas
2023-09-19 10:19               ` Wolfram Sang
2023-09-19 12:38                 ` Yann Sionneau
2023-09-19 14:51                   ` Catalin Marinas [this message]
2023-09-19 14:55                     ` Wolfram Sang
2023-09-19 18:54                     ` Jan Bottorff
2023-09-19 21:05                       ` Serge Semin
2023-09-20  9:08                         ` Wolfram Sang
2023-09-20 13:27                           ` Yann Sionneau
2023-09-20 19:14                             ` Jan Bottorff
2023-09-25 12:54                               ` Serge Semin
2023-09-25 19:39                                 ` Jan Bottorff
2023-09-27 19:38                                   ` Wolfram Sang
2023-09-29  8:48                                     ` Jarkko Nikula
2023-10-26 11:18                                       ` Wolfram Sang
2023-10-31  0:12                                         ` Jan Bottorff
2023-10-31  5:51                                           ` Wolfram Sang
2023-10-31  8:44                                           ` Yann Sionneau
2023-10-31 12:10                                             ` Jarkko Nikula
2023-10-31 13:06                                               ` Serge Semin
2023-11-01 16:51                                                 ` Jan Bottorff
2023-09-20 11:03                         ` Catalin Marinas
2023-09-20 10:44                       ` Catalin Marinas
2023-09-20 11:05                         ` Catalin Marinas

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