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[31.46.245.48]) by smtp.gmail.com with ESMTPSA id r27-20020a17090638db00b0099cf9bf4c98sm567225ejd.8.2023.10.03.00.28.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Oct 2023 00:28:35 -0700 (PDT) Sender: Ingo Molnar Date: Tue, 3 Oct 2023 09:28:33 +0200 From: Ingo Molnar To: Nathan Chancellor Cc: Dave Hansen , linux-kernel@vger.kernel.org, x86@kernel.org, acdunlap@google.com, ashok.raj@intel.com, bp@alien8.de, david@redhat.com, dionnaglaze@google.com, hpa@zytor.com, jacobhxu@google.com, jgross@suse.com, jroedel@suse.de, khalid.elmously@canonical.com, kim.phillips@amd.com, kirill.shutemov@linux.intel.com, llvm@lists.linux.dev, luto@kernel.org, mingo@redhat.com, nikunj@amd.com, peterz@infradead.org, pgonda@google.com, rientjes@google.com, rppt@kernel.org, seanjc@google.com, tglx@linutronix.de, thomas.lendacky@amd.com Subject: Re: [PATCH] x86/boot: Move x86_cache_alignment initialization to correct spot Message-ID: References: <20231002200426.GA4127272@dev-arch.thelio-3990X> <20231002220045.1014760-1-dave.hansen@linux.intel.com> <20231002222402.GA486933@dev-arch.thelio-3990X> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231002222402.GA486933@dev-arch.thelio-3990X> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * Nathan Chancellor wrote: > On Mon, Oct 02, 2023 at 03:00:45PM -0700, Dave Hansen wrote: > > c->x86_cache_alignment is initialized from c->x86_clflush_size. > > However, commit fbf6449f84bf moved c->x86_clflush_size initialization > > to later in boot without moving the c->x86_cache_alignment assignment. > > > > This presumably left c->x86_cache_alignment set to zero for longer > > than it should be. > > > > The result was an oops on 32-bit kernels while accessing a pointer > > at 0x20. The 0x20 came from accessing a structure member at offset > > 0x10 (buffer->cpumask) from a ZERO_SIZE_PTR=0x10. kmalloc() can > > evidently return ZERO_SIZE_PTR when it's given 0 as its alignment > > requirement. > > > > Move the c->x86_cache_alignment initialization to be after > > c->x86_clflush_size has an actual value. > > > > Fixes: fbf6449f84bf ("x86/sev-es: Set x86_virt_bits to the correct value straight away, instead of a two-phase approach") > > Cc: Adam Dunlap > > Cc: Ingo Molnar > > Cc: Jacob Xu > > Link: https://lore.kernel.org/all/20231002200426.GA4127272@dev-arch.thelio-3990X/ > > Tested-by: Nathan Chancellor > > Thanks for the quick fix! Thanks for the quick testing - I've applied this fix on top of fbf6449f84bf in tip:x86/mm. Dave, I've added your SOB - let me know if that's not OK: Signed-off-by: Dave Hansen Thanks, Ingo