Re: [PATCH v2 5/7] riscv: dts: sophgo: cv180x: Add gpio devices

Chen Wang
2023-10-12T12:52:59Z

On 2023/10/9 19:26, Inochi Amaoto wrote:
> Add common GPIO devices for the CV180x and CV181x soc.
>
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> ---
> arch/riscv/boot/dts/sophgo/cv180x.dtsi | 72 ++++++++++++++++++++++++++
> 1 file changed, 72 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
> index ffaf51724c98..64ffb23d3626 100644
> --- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
> @@ -53,6 +53,78 @@ soc {
> dma-noncoherent;
> ranges;
>
> + gpio0: gpio@3020000 {
> + compatible = "snps,dw-apb-gpio";
> + reg = <0x3020000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + porta: gpio-controller@0 {
> + compatible = "snps,dw-apb-gpio-port";
> + gpio-controller;
> + #gpio-cells = <2>;
> + ngpios = <32>;
> + reg = <0>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + gpio1: gpio@3021000 {
> + compatible = "snps,dw-apb-gpio";
> + reg = <0x3021000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + portb: gpio-controller@0 {
> + compatible = "snps,dw-apb-gpio-port";
> + gpio-controller;
> + #gpio-cells = <2>;
> + ngpios = <32>;
> + reg = <0>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + gpio2: gpio@3022000 {
> + compatible = "snps,dw-apb-gpio";
> + reg = <0x3022000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + portc: gpio-controller@0 {
> + compatible = "snps,dw-apb-gpio-port";
> + gpio-controller;
> + #gpio-cells = <2>;
> + ngpios = <32>;
> + reg = <0>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + gpio3: gpio@3023000 {
> + compatible = "snps,dw-apb-gpio";
> + reg = <0x3023000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + portd: gpio-controller@0 {
> + compatible = "snps,dw-apb-gpio-port";
> + gpio-controller;
> + #gpio-cells = <2>;
> + ngpios = <32>;
> + reg = <0>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> uart0: serial@4140000 {
> compatible = "snps,dw-apb-uart";
> reg = <0x04140000 0x100>;
LGTM

Acked-by: Chen Wang <unicorn_wang@outlook.com>

Thanks,

Chen

> --
> 2.42.0
>