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Date:   Fri, 20 Oct 2023 16:08:27 +0800
From:   Yu-Chien Peter Lin <peterlin@andestech.com>
To:     Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Subject: Re: [PATCH v2 05/10] dt-bindings: riscv: Add andestech,cpu-intc to
 interrupt-controller
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References: <20231019135905.3658215-1-peterlin@andestech.com>
 <ba3ac1b2-d924-44cb-97dd-6af65a1db7a8@linaro.org>
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On Fri, Oct 20, 2023 at 09:00:03AM +0200, Krzysztof Kozlowski wrote:
> On 19/10/2023 15:59, Yu Chien Peter Lin wrote:
> > Add "andestech,cpu-intc" compatible string for Andes INTC which
> > provides Andes-specific IRQ chip functions.
> > 
> > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> > ---
> > Changes v1 -> v2:
> >   - New patch
> > ---
> >  Documentation/devicetree/bindings/riscv/cpus.yaml | 4 +++-
> >  1 file changed, 3 insertions(+), 1 deletion(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > index 97e8441eda1c..5b216e11c69f 100644
> > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > @@ -99,7 +99,9 @@ properties:
> >          const: 1
> >  
> >        compatible:
> > -        const: riscv,cpu-intc
> > +        enum:
> > +          - riscv,cpu-intc
> > +          - andestech,cpu-intc
> 
> Keep alphabetical order. Do not add stuff to the end of the lists. This
> is a generic rule. Everywhere.

Hi Krzysztof,

Thansk for pointing this out.
Will fix this in PATCH v3.

Best regards,
Peter Lin

> Best regards,
> Krzysztof
>