From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6B88C25B6F for ; Thu, 26 Oct 2023 08:24:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344542AbjJZIY7 (ORCPT ); Thu, 26 Oct 2023 04:24:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53284 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344475AbjJZIYz (ORCPT ); Thu, 26 Oct 2023 04:24:55 -0400 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5FEEEB8; Thu, 26 Oct 2023 01:24:52 -0700 (PDT) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 39Q8MUGX059449; Thu, 26 Oct 2023 16:22:30 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from APC323 (10.0.12.98) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Thu, 26 Oct 2023 16:22:26 +0800 Date: Thu, 26 Oct 2023 16:22:22 +0800 From: Yu-Chien Peter Lin To: Conor Dooley CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v3 RESEND 10/13] dt-bindings: riscv: Add Andes PMU extension description Message-ID: References: <20231023004100.2663486-1-peterlin@andestech.com> <20231023004100.2663486-11-peterlin@andestech.com> <20231023-spectacle-module-0516fb35995a@spud> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20231023-spectacle-module-0516fb35995a@spud> User-Agent: Mutt/2.2.10 (2023-03-25) X-Originating-IP: [10.0.12.98] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 39Q8MUGX059449 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Conor, On Mon, Oct 23, 2023 at 01:03:53PM +0100, Conor Dooley wrote: > On Mon, Oct 23, 2023 at 08:40:57AM +0800, Yu Chien Peter Lin wrote: > > Document the ISA string for Andes Technology performance monitor > > extension which provides counter overflow interrupt and mode > > filtering mechanisms. > > > > Signed-off-by: Yu Chien Peter Lin > > --- > > Changes v2 -> v3: > > - New patch > > --- > > Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++ > > 1 file changed, 7 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml > > index 5e9291d258d5..e0694e2adbc2 100644 > > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml > > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml > > @@ -246,6 +246,13 @@ properties: > > in commit 2e5236 ("Ztso is now ratified.") of the > > riscv-isa-manual. > > > > + - const: xandespmu > > + description: > > + The Andes Technology performance monitor extension for counter overflow > > + and privilege mode filtering. For more details, see Counter Related > > + Registers in the AX45MP datasheet. > > + https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf > > Does/will this PMU function identically on the other CPUs that support it? Yes, I can confirm that. Thanks for the review. Best regards, Peter Lin > I assume the answer is yes. > > Cheers, > Conor. > > > + > > - const: xtheadpmu > > description: > > The T-Head performance monitor extension for counter overflow. For more > > -- > > 2.34.1 > >