From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A68E1C4332F for ; Wed, 1 Nov 2023 15:35:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343655AbjKAPfU (ORCPT ); Wed, 1 Nov 2023 11:35:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48176 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234553AbjKAPfQ (ORCPT ); Wed, 1 Nov 2023 11:35:16 -0400 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 150B7102; Wed, 1 Nov 2023 08:35:10 -0700 (PDT) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 67AE3C433C9; Wed, 1 Nov 2023 15:35:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1698852909; bh=bbdrSxFMrsXv8i5RW4uSoBXIoUFMBluPi9Yoa790odM=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=rgJY1V2HKsWnaXdqbPjdfzpglTtq4dcJLMF+pW0xil4K7rwUmLxqh1iiY/XXQOjXM M19pPpzwc1M6I8QCWhA1O5ynJKE2lWLDj1CWSGJAW+n2OEagaQkhjs0A964+/7Rk1Z s1svrJnFT0glrtxFNZktZ0K1STk+LOAhF01HCtPqYkAjde+kWePYT/uNA7buXZwuRe uqIJI9OiyIs+0BodAgzGbRjZthhdhCTKL2vkMt5vAoC8SNHr2AODXhPZI+y+pwpsTI sgygKOQ+nEVsJ+EXqCWQEfLur/RiWcWDx7MHGphZBGPQh7yxxHDq0ot/N/Cr1MFhnP BZ8cyZlqOvbVQ== Date: Wed, 1 Nov 2023 23:22:52 +0800 From: Jisheng Zhang To: Charlie Jenkins Cc: Palmer Dabbelt , Conor Dooley , Samuel Holland , David Laight , Xiao Wang , Evan Green , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, Paul Walmsley , Albert Ou , Arnd Bergmann , Conor Dooley Subject: Re: [PATCH v9 3/5] riscv: Checksum header Message-ID: References: <20231031-optimize_checksum-v9-0-ea018e69b229@rivosinc.com> <20231031-optimize_checksum-v9-3-ea018e69b229@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20231031-optimize_checksum-v9-3-ea018e69b229@rivosinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Oct 31, 2023 at 05:18:53PM -0700, Charlie Jenkins wrote: > Provide checksum algorithms that have been designed to leverage riscv > instructions such as rotate. In 64-bit, can take advantage of the larger > register to avoid some overflow checking. > > Signed-off-by: Charlie Jenkins > Acked-by: Conor Dooley > --- > arch/riscv/include/asm/checksum.h | 81 +++++++++++++++++++++++++++++++++++++++ > 1 file changed, 81 insertions(+) > > diff --git a/arch/riscv/include/asm/checksum.h b/arch/riscv/include/asm/checksum.h > new file mode 100644 > index 000000000000..3d77cac338fe > --- /dev/null > +++ b/arch/riscv/include/asm/checksum.h > @@ -0,0 +1,81 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Checksum routines > + * > + * Copyright (C) 2023 Rivos Inc. > + */ > +#ifndef __ASM_RISCV_CHECKSUM_H > +#define __ASM_RISCV_CHECKSUM_H > + > +#include > +#include > + > +#define ip_fast_csum ip_fast_csum > + > +/* Define riscv versions of functions before importing asm-generic/checksum.h */ > +#include > + > +/* > + * Quickly compute an IP checksum with the assumption that IPv4 headers will > + * always be in multiples of 32-bits, and have an ihl of at least 5. > + * @ihl is the number of 32 bit segments and must be greater than or equal to 5. > + * @iph is assumed to be word aligned given that NET_IP_ALIGN is set to 2 on > + * riscv, defining IP headers to be aligned. > + */ > +static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl) > +{ > + unsigned long csum = 0; > + int pos = 0; > + > + do { > + csum += ((const unsigned int *)iph)[pos]; > + if (IS_ENABLED(CONFIG_32BIT)) > + csum += csum < ((const unsigned int *)iph)[pos]; > + } while (++pos < ihl); > + > + /* > + * ZBB only saves three instructions on 32-bit and five on 64-bit so not > + * worth checking if supported without Alternatives. > + */ > + if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && > + IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) { > + unsigned long fold_temp; > + > + asm_volatile_goto(ALTERNATIVE("j %l[no_zbb]", "nop", 0, > + RISCV_ISA_EXT_ZBB, 1) This looks like a open coding of riscv_has_extension_*, so if we use the it, the code could be rewritten as: if (riscv_has_extension_likely(RISCV_ISA_EXT_ZBB)) { if (32bit) { asm(...) } else { asm(...) } return csum >> 16; } #ifndef CONFIG_32BIT csum += ror64(csum, 32); csum >>= 32; #endif return csum_fold((__force __wsum)csum); The code readability is improved and make it a bit easier to refactor the asm(...) code in the future. And IMHO, the generated code should be the same. Thanks > > + : > + : > + : > + : no_zbb); > + > + if (IS_ENABLED(CONFIG_32BIT)) { > + asm(".option push \n\ > + .option arch,+zbb \n\ > + not %[fold_temp], %[csum] \n\ > + rori %[csum], %[csum], 16 \n\ > + sub %[csum], %[fold_temp], %[csum] \n\ > + .option pop" > + : [csum] "+r" (csum), [fold_temp] "=&r" (fold_temp)); > + } else { > + asm(".option push \n\ > + .option arch,+zbb \n\ > + rori %[fold_temp], %[csum], 32 \n\ > + add %[csum], %[fold_temp], %[csum] \n\ > + srli %[csum], %[csum], 32 \n\ > + not %[fold_temp], %[csum] \n\ > + roriw %[csum], %[csum], 16 \n\ > + subw %[csum], %[fold_temp], %[csum] \n\ > + .option pop" > + : [csum] "+r" (csum), [fold_temp] "=&r" (fold_temp)); > + } > + return csum >> 16; > + } > +no_zbb: > +#ifndef CONFIG_32BIT > + csum += ror64(csum, 32); > + csum >>= 32; > +#endif > + return csum_fold((__force __wsum)csum); > +} > + > +#endif /* __ASM_RISCV_CHECKSUM_H */ > > -- > 2.34.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv