* [PATCH] cxl/region: fix x9 interleave typo
[not found] <CGME20231103201835uscas1p29ca7f76ed5e4c829bfb022a040202d73@uscas1p2.samsung.com>
@ 2023-11-03 20:18 ` Jim Harris
2023-11-03 20:28 ` Dave Jiang
2023-11-06 18:27 ` fan
0 siblings, 2 replies; 3+ messages in thread
From: Jim Harris @ 2023-11-03 20:18 UTC (permalink / raw)
To: Davidlohr Bueso, Jonathan Cameron, Dave Jiang, Alison Schofield,
Vishal Verma, Ira Weiny, Dan Williams, Fan Ni,
linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org
CXL supports x3, x6 and x12 - not x9.
Fixes: 80d10a6cee050 ("cxl/region: Add interleave geometry attributes")
Signed-off-by: Jim Harris <jim.harris@samsung.com>
---
drivers/cxl/core/region.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
index 6d63b8798c29..d295b3488e4a 100644
--- a/drivers/cxl/core/region.c
+++ b/drivers/cxl/core/region.c
@@ -403,7 +403,7 @@ static ssize_t interleave_ways_store(struct device *dev,
return rc;
/*
- * Even for x3, x9, and x12 interleaves the region interleave must be a
+ * Even for x3, x6, and x12 interleaves the region interleave must be a
* power of 2 multiple of the host bridge interleave.
*/
if (!is_power_of_2(val / cxld->interleave_ways) ||
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] cxl/region: fix x9 interleave typo
2023-11-03 20:18 ` [PATCH] cxl/region: fix x9 interleave typo Jim Harris
@ 2023-11-03 20:28 ` Dave Jiang
2023-11-06 18:27 ` fan
1 sibling, 0 replies; 3+ messages in thread
From: Dave Jiang @ 2023-11-03 20:28 UTC (permalink / raw)
To: Jim Harris, Davidlohr Bueso, Jonathan Cameron, Alison Schofield,
Vishal Verma, Ira Weiny, Dan Williams, Fan Ni,
linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org
On 11/3/23 13:18, Jim Harris wrote:
> CXL supports x3, x6 and x12 - not x9.
>
> Fixes: 80d10a6cee050 ("cxl/region: Add interleave geometry attributes")
> Signed-off-by: Jim Harris <jim.harris@samsung.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Given it's a fix to a comment, the fixes tag is probably not necessary since it's not a code bug to backport to stable.
> ---
> drivers/cxl/core/region.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index 6d63b8798c29..d295b3488e4a 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -403,7 +403,7 @@ static ssize_t interleave_ways_store(struct device *dev,
> return rc;
>
> /*
> - * Even for x3, x9, and x12 interleaves the region interleave must be a
> + * Even for x3, x6, and x12 interleaves the region interleave must be a
> * power of 2 multiple of the host bridge interleave.
> */
> if (!is_power_of_2(val / cxld->interleave_ways) ||
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] cxl/region: fix x9 interleave typo
2023-11-03 20:18 ` [PATCH] cxl/region: fix x9 interleave typo Jim Harris
2023-11-03 20:28 ` Dave Jiang
@ 2023-11-06 18:27 ` fan
1 sibling, 0 replies; 3+ messages in thread
From: fan @ 2023-11-06 18:27 UTC (permalink / raw)
To: Jim Harris
Cc: Davidlohr Bueso, Jonathan Cameron, Dave Jiang, Alison Schofield,
Vishal Verma, Ira Weiny, Dan Williams, Fan Ni,
linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org
On Fri, Nov 03, 2023 at 08:18:34PM +0000, Jim Harris wrote:
> CXL supports x3, x6 and x12 - not x9.
>
> Fixes: 80d10a6cee050 ("cxl/region: Add interleave geometry attributes")
> Signed-off-by: Jim Harris <jim.harris@samsung.com>
> ---
Reviewed-by: Fan Ni <fan.ni@samsung.com>
> drivers/cxl/core/region.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index 6d63b8798c29..d295b3488e4a 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -403,7 +403,7 @@ static ssize_t interleave_ways_store(struct device *dev,
> return rc;
>
> /*
> - * Even for x3, x9, and x12 interleaves the region interleave must be a
> + * Even for x3, x6, and x12 interleaves the region interleave must be a
> * power of 2 multiple of the host bridge interleave.
> */
> if (!is_power_of_2(val / cxld->interleave_ways) ||
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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[not found] <CGME20231103201835uscas1p29ca7f76ed5e4c829bfb022a040202d73@uscas1p2.samsung.com>
2023-11-03 20:18 ` [PATCH] cxl/region: fix x9 interleave typo Jim Harris
2023-11-03 20:28 ` Dave Jiang
2023-11-06 18:27 ` fan
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