From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4208DC61D9B for ; Wed, 22 Nov 2023 09:18:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235286AbjKVJSD (ORCPT ); Wed, 22 Nov 2023 04:18:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48978 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235234AbjKVJRo (ORCPT ); Wed, 22 Nov 2023 04:17:44 -0500 Received: from mail-ed1-x529.google.com (mail-ed1-x529.google.com [IPv6:2a00:1450:4864:20::529]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EE90A35A6 for ; Wed, 22 Nov 2023 01:02:40 -0800 (PST) Received: by mail-ed1-x529.google.com with SMTP id 4fb4d7f45d1cf-548b54ed16eso4408438a12.0 for ; Wed, 22 Nov 2023 01:02:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700643759; x=1701248559; darn=vger.kernel.org; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=WVAJl9uglbvTGhaLo4viphdxTulyQeTTf7hqzg6Dhck=; b=JRtUjga6RbDydNJa8htW2OfRuj9AatnPpcBEZ4TqzDvLHu/1LaXBh2PEv2K2xK9DP7 zkAbBwsJ9TKSLuZpPF+dr0aQyUx8L+YkOi3KsGu6wPPHc4j540cMi5Tt1Juyu0Zv9G6G coZAZmXJzVdrh/+CPG43ZMGhcqRwUxLeHeBupKBbOr1Xqr/R1Lfu3cytzvYdNHrni3IS 6d8InxX6TLoNH+iEAEA/lMtrWmMPnLEG++w7Cn1RZtK1BPuuzAqEcOwQlRsAJ5N+y8ke 3q8wLfjrJrlIlrutsr6tDdBJhHwy3aPdolmYD6U4pif9H68hWwzq1j6cMByiJpDSjWqz qkSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700643759; x=1701248559; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=WVAJl9uglbvTGhaLo4viphdxTulyQeTTf7hqzg6Dhck=; b=n2YElz/Dwgbl2tTsJOhUlhKLCNZZPprGjOaKHhSJqYItgUrpdrTyUZXeWgvV6ZAzVq BVdgIRgXwB932MrfsGvQOiHy9+59qfaNEbEDiMph52xlHh5IbrEEUUY1aXAPQXhg/xja DaoZmwOy4AepnEOa2ta06OmusM197xTniN8iT0M19reEC31NU3WneLNFOdsBd4bpZ2VM 3WkyD+RB2Z1j9J9E15lwlW+j3cqy2wb3odUGdFjI5KdgCT5ta8ayIWzNY35dcjoIXajn +KW9Pk+I5OfA2Y/gE5OsnOUsKK+N1WYozd/ej/vYN1VjN1849UEg7DDPEx0fqBL3AiAM dkxQ== X-Gm-Message-State: AOJu0YwVa6qL+hZiaseE+BO9QaRCXjG6B6Wdgxd6fVstxIPaInl30Z2I KdJIfKyLypdkRDz/JtC/mZP2Ew== X-Google-Smtp-Source: AGHT+IHUvNB0p3pjPTLNAuD5yzEhkWruucScfm3SgkoaPdwhYN1nGHxSGHwPAZE2ViijHNFsaTVXGA== X-Received: by 2002:a50:fb9a:0:b0:53e:58fd:9600 with SMTP id e26-20020a50fb9a000000b0053e58fd9600mr1299683edq.36.1700643759360; Wed, 22 Nov 2023 01:02:39 -0800 (PST) Received: from linaro.org ([86.123.99.122]) by smtp.gmail.com with ESMTPSA id m24-20020a50ef18000000b00548699fa102sm4909449eds.83.2023.11.22.01.02.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Nov 2023 01:02:38 -0800 (PST) Date: Wed, 22 Nov 2023 11:02:36 +0200 From: Abel Vesa To: Can Guo Cc: bvanassche@acm.org, mani@kernel.org, stanley.chu@mediatek.com, adrian.hunter@intel.com, beanhuo@micron.com, avri.altman@wdc.com, junwoo80.lee@samsung.com, martin.petersen@oracle.com, Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Johan Hovold , Dmitry Baryshkov , "open list:ARM/QUALCOMM SUPPORT" , "open list:GENERIC PHY FRAMEWORK" , open list Subject: Re: [PATCH v3 08/11] phy: qualcomm: phy-qcom-qmp-ufs: Rectify SM8550 UFS HS-G4 PHY Settings Message-ID: References: <1700637042-11104-1-git-send-email-quic_cang@quicinc.com> <1700637042-11104-9-git-send-email-quic_cang@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1700637042-11104-9-git-send-email-quic_cang@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 23-11-21 23:10:39, Can Guo wrote: > The registers, which are being touched in current SM8550 UFS PHY settings, > and the values being programmed are mainly the ones working for HS-G4 mode, > meanwhile, there are also a few ones somehow taken from HS-G5 PHY settings. > However, even consider HS-G4 mode only, some of them are incorrect and some > are missing. Rectify the HS-G4 PHY settings by strictly aligning with the > SM8550 UFS PHY Hardware Programming Guide suggested HS-G4 PHY settings. > > Fixes: 1679bfef906f ("phy: qcom-qmp-ufs: Add SM8550 support") > Signed-off-by: Can Guo Reviewed-by: Abel Vesa > --- > .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 3 +++ > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 28 +++++++++++++++------- > 2 files changed, 22 insertions(+), 9 deletions(-) > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h > index 15bcb4b..674f158 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h > @@ -10,9 +10,12 @@ > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30 > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34 > +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c > +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108 > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08 > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10 > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4 > #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178 > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208 > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c > index 3927eba..ad91f92 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c > @@ -658,22 +658,26 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = { > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14), > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f), > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06), > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c), > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a), > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14), > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99), > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07), > +}; > + > +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = { > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44), > }; > > static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = { > - QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05), > QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c), > }; > > static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = { > - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2, 0x0c), > - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x0f), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c), > QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e), > > QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2), > @@ -696,6 +700,8 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = { > QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), > QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b), > QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02), > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04), > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04), > }; > > struct qmp_ufs_offsets { > @@ -1157,6 +1163,10 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = { > .pcs = sm8550_ufsphy_pcs, > .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs), > }, > + .tbls_hs_b = { > + .serdes = sm8550_ufsphy_hs_b_serdes, > + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes), > + }, > .clk_list = sdm845_ufs_phy_clk_l, > .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), > .vreg_list = qmp_phy_vreg_l, > -- > 2.7.4 >