[PATCH v3] iommu: map reserved memory as cacheable if device is coherent

[PATCH v3] iommu: map reserved memory as cacheable if device is coherent

[Laurentiu Tudor]

Check if the device is marked as DMA coherent in the DT and if so,
map its reserved memory as cacheable in the IOMMU.
This fixes the recently added IOMMU reserved memory support which
uses IOMMU_RESV_DIRECT without properly building the PROT for the
mapping.

Fixes: a5bf3cfce8cb ("iommu: Implement of_iommu_get_resv_regions()")
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
---
Changes in v3:
 - added Acked-by tag (Thierry)

Changes in v2:
 - added Reviewed-by tag (Jason)

 drivers/iommu/of_iommu.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c
index 157b286e36bf..5b3631ba5a45 100644
--- a/drivers/iommu/of_iommu.c
+++ b/drivers/iommu/of_iommu.c
@@ -254,6 +254,9 @@ void of_iommu_get_resv_regions(struct device *dev, struct list_head *list)
 				phys_addr_t iova;
 				size_t length;
 
+				if (of_dma_is_coherent(dev->of_node))
+					prot |= IOMMU_CACHE;
+
 				maps = of_translate_dma_region(np, maps, &iova, &length);
 				type = iommu_resv_region_get_type(dev, &phys, iova, length);
 
-- 
2.17.1

Re: [PATCH v3] iommu: map reserved memory as cacheable if device is coherent

[Laurentiu Tudor]

Hello,

Any chance of having this picked up? It is the last missing bit to fix 
booting vanilla images on some NXP platforms (Layerscape LX2160A, 
LS2088A, LS1088A) given that the bootloader side of things [1] was accepted.
Thank you!

[1] https://patchwork.ozlabs.org/project/uboot/list/?series=375154&state=*

---
Best Regards, Laurentiu

On 9/26/2023 6:26 PM, Laurentiu Tudor wrote:
> Check if the device is marked as DMA coherent in the DT and if so,
> map its reserved memory as cacheable in the IOMMU.
> This fixes the recently added IOMMU reserved memory support which
> uses IOMMU_RESV_DIRECT without properly building the PROT for the
> mapping.
> 
> Fixes: a5bf3cfce8cb ("iommu: Implement of_iommu_get_resv_regions()")
> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
> Acked-by: Thierry Reding <treding@nvidia.com>
> ---
> Changes in v3:
>   - added Acked-by tag (Thierry)
> 
> Changes in v2:
>   - added Reviewed-by tag (Jason)
> 
>   drivers/iommu/of_iommu.c | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c
> index 157b286e36bf..5b3631ba5a45 100644
> --- a/drivers/iommu/of_iommu.c
> +++ b/drivers/iommu/of_iommu.c
> @@ -254,6 +254,9 @@ void of_iommu_get_resv_regions(struct device *dev, struct list_head *list)
>   				phys_addr_t iova;
>   				size_t length;
>   
> +				if (of_dma_is_coherent(dev->of_node))
> +					prot |= IOMMU_CACHE;
> +
>   				maps = of_translate_dma_region(np, maps, &iova, &length);
>   				type = iommu_resv_region_get_type(dev, &phys, iova, length);
>   

Re: [PATCH v3] iommu: map reserved memory as cacheable if device is coherent

[Joerg Roedel]

On Tue, Sep 26, 2023 at 06:26:00PM +0300, Laurentiu Tudor wrote:
>  drivers/iommu/of_iommu.c | 3 +++
>  1 file changed, 3 insertions(+)

Applied, thanks.