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Date:   Thu, 14 Dec 2023 11:09:41 +0800
From:   Tzung-Bi Shih <tzungbi@kernel.org>
To:     Mark Hasemeyer <markhas@chromium.org>
Cc:     LKML <linux-kernel@vger.kernel.org>,
        Raul Rangel <rrangel@chromium.org>,
        Benson Leung <bleung@chromium.org>,
        Bhanu Prakash Maiya <bhanumaiya@chromium.org>,
        Chen-Yu Tsai <wenst@chromium.org>,
        Guenter Roeck <groeck@chromium.org>,
        Prashant Malani <pmalani@chromium.org>,
        Rob Barnes <robbarnes@google.com>,
        chrome-platform@lists.linux.dev
Subject: Re: [PATCH v1 6/6] platform/chrome: cros_ec: Use PM subsystem to
 manage wakeirq
Message-ID: <ZXpx9esFooSgq11q@google.com>
References: <20231213110009.v1.1.Ifd0903f1c351e84376d71dbdadbd43931197f5ea@changeid>
 <20231213110009.v1.6.Ieee574a0e94fbaae01fd6883ffe2ceeb98d7df28@changeid>
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On Wed, Dec 13, 2023 at 11:00:24AM -0700, Mark Hasemeyer wrote:
> The cros ec driver is manually managing the wake irq by calling
> enable_irq_wake/disable_irq_wake during suspend/resume.
> 
> Modify the driver to use the power management subsystem to manage the
> wakeirq.
> 
> The wake capability of the interrupt is provided by the underlying
> firmware/device tree. Some Chromebooks rely solely on the ec_sync pin to
> wake the AP but they do not specify the interrupt as wake capable in the
> ACPI _CRS or device tree. For LPC/ACPI based systems a DMI quirk is
> introduced listing boards whose firmware should not be trusted to
> provide correct wake capable values.
> 
> The irq wake logic was added on an interface basis (lpc, spi, uart) as
> opposed to adding it to cros_ec.c because the i2c subsystem already does
> this work on our behalf.

It looks to me the patch combines multiple changes.  Please separate them into
smaller pieces for reviewing easier.

Another confusing about the patch subject: "6/6"?  Is it a series?  I don't
see the cover letter.