* Re: Bug: After a 'warm' reboot the disk is missing (not detected by the bios) on a HP t640 [not found] <DB3PR0502MB999347F512ECFDBE3BFA9941B697A@DB3PR0502MB9993.eurprd05.prod.outlook.com> @ 2023-12-20 16:47 ` Sean Christopherson 2023-12-28 12:39 ` Ben Mesman | Spark Narrowcasting 0 siblings, 1 reply; 9+ messages in thread From: Sean Christopherson @ 2023-12-20 16:47 UTC (permalink / raw) To: Ben Mesman | Spark Narrowcasting Cc: Thomas Gleixner, Ingo Molnar, Borislav Petkov, Dave Hansen, x86, linux-kernel +LKML and other maintainers On Tue, Dec 19, 2023, Ben Mesman | Spark Narrowcasting wrote: > Hello, > > First of all, sorry if this is not the proper way of submitting a patch. > According to the get_maintainer.pl-script for arch/x86/kernel/reboot.c you > are one of the maintainers of that file. If the patch should go to a > different maintainer, can you direct me to either the right person, or the > right location to find such a person? Please don't send private mails. Kudos for using get_maintainer.pl, but a demerit for not Cc'ing the mailing lists :-) https://people.kernel.org/tglx/notes-about-netiquette > I recently started upgrading some of my remote managed thin-clients from a > 5.15.x kernel to a 6.1.x kernel. When rebooting with the new(er) kernel, the > HP t640 clients failed. The problem is that after the warm reboot, the BIOS > is unable to locate the internal storage (so it can't boot a valid OS). > > With some digging around I found that adding "reboot=p" will solve the > problem, but because the systems are remote managed, I am unable to add this > boot-parameter in any straightforward way. > > I reported the issue as a bug in Debian > (https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=1056056) but to get it > solved permanently, they told me to try and get a patch/solution upstream. > > What worked for me is the attached patch, which adds a reboot-quirk for the > affected systems. I can submit this also as a pull-request (I think) but I > don't know the proper way of submitting a pull-request, the last one I did > was more than 10 years ago. > > Kind regards, > Ben Mesman > ben@sparknarrowcasting.nl > > diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c > index 830425e6d38e..d63cc44a1117 100644 > --- a/arch/x86/kernel/reboot.c > +++ b/arch/x86/kernel/reboot.c > @@ -468,6 +468,14 @@ static const struct dmi_system_id reboot_dmi_table[] __initconst = { > DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq"), > }, > }, > + { /* Handle problems with rebooting HP t640 thin-clients */ > + .callback = set_pci_reboot, > + .ident = "HP t640", > + .matches = { > + DMI_MATCH(DMI_SYS_VENDOR, "HP"), > + DMI_MATCH(DMI_PRODUCT_NAME, "HP t640 Thin Client"), > + }, > + }, I'm not familiar with this code (I'm not actually a maintainer/reviewer for this code, by default get_maintainer.pl Cc's people that have recently modified the file in question), but this looks like a hack to workaround a bug elsewhere. All of these quirks are obviously workarounds for some kind of bug, but AFAICT the quirks are to workaround hardware or firmware bugs, not kernel bugs. Since 5.15.x kernels worked, odds are good a bug was introduced between 5.15 and 6.1, i.e. that this is fudging around a kernel bug that can and should be fixed. Are you able to bisect the kernel between 6.1 and 5.15 to try and pinpoint an exact commit that introduced the problem? ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: Bug: After a 'warm' reboot the disk is missing (not detected by the bios) on a HP t640 2023-12-20 16:47 ` Bug: After a 'warm' reboot the disk is missing (not detected by the bios) on a HP t640 Sean Christopherson @ 2023-12-28 12:39 ` Ben Mesman | Spark Narrowcasting 2024-01-02 17:58 ` Sean Christopherson 0 siblings, 1 reply; 9+ messages in thread From: Ben Mesman | Spark Narrowcasting @ 2023-12-28 12:39 UTC (permalink / raw) To: Sean Christopherson Cc: Thomas Gleixner, Ingo Molnar, Borislav Petkov, Dave Hansen, x86@kernel.org, linux-kernel@vger.kernel.org > Please don't send private mails. Kudos for using get_maintainer.pl, but a demerit > for not Cc'ing the mailing lists :-) > > https://people.kernel.org/tglx/notes-about-netiquette Definitely saving that in my URLs-cache. Might need it again in a few years :-) (last time I needed it was about 10 years ago) > > I recently started upgrading some of my remote managed thin-clients from a > > 5.15.x kernel to a 6.1.x kernel. When rebooting with the new(er) kernel, the > > HP t640 clients failed. The problem is that after the warm reboot, the BIOS > > is unable to locate the internal storage (so it can't boot a valid OS). > > > > With some digging around I found that adding "reboot=p" will solve the > > problem, but because the systems are remote managed, I am unable to add this > > boot-parameter in any straightforward way. [snip] > I'm not familiar with this code (I'm not actually a maintainer/reviewer for this > code, by default get_maintainer.pl Cc's people that have recently modified the > file in question), but this looks like a hack to workaround a bug elsewhere. > > All of these quirks are obviously workarounds for some kind of bug, but AFAICT > the quirks are to workaround hardware or firmware bugs, not kernel bugs. Since > 5.15.x kernels worked, odds are good a bug was introduced between 5.15 and 6.1, > i.e. that this is fudging around a kernel bug that can and should be fixed. > > Are you able to bisect the kernel between 6.1 and 5.15 to try and pinpoint an > exact commit that introduced the problem? That took a few days, but resulted in the following: 4be33cf187036744b4ed84824e7157cfc09c6f4c is the first bad commit commit 4be33cf187036744b4ed84824e7157cfc09c6f4c Author: Fred Ai <fred.ai@bayhubtech.com> Date: Mon Dec 20 20:09:40 2021 -0800 mmc: sdhci-pci-o2micro: Improve card input timing at SDR104/HS200 mode Card input timing is margin, need to adjust the hold timing of card input. Signed-off-by: Fred Ai <fred.ai@bayhubtech.com> Link: https://lore.kernel.org/r/20211221040940.484-1-fred.ai@bayhubtech.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> drivers/mmc/host/sdhci-pci-o2micro.c | 57 ++++++++++++++++++++++++++++++------ 1 file changed, 48 insertions(+), 9 deletions(-) I'm not sure how this code impacts this device, but it does contain a "HS200 MMC card": $ dmesg | grep mmc [ 1.044708] mmc0: emmc 1.8v flag is set, force 1.8v signaling voltage [ 1.044937] mmc0: SDHCI controller on PCI [0000:01:00.0] using ADMA [ 2.120632] mmc0: new HS200 MMC card at address 0001 [ 2.122912] mmcblk0: mmc0:0001 hA8aP> 14.7 GiB [ 2.124810] mmcblk0: p1 p2 p3 I can provide more info on the hardware, which is also available in https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=1056056 -- Kind regards, Ben Mesman ben@sparknarrowcasting.nl ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: Bug: After a 'warm' reboot the disk is missing (not detected by the bios) on a HP t640 2023-12-28 12:39 ` Ben Mesman | Spark Narrowcasting @ 2024-01-02 17:58 ` Sean Christopherson 2024-01-03 12:23 ` 回复: " Fred Ai(WH) 0 siblings, 1 reply; 9+ messages in thread From: Sean Christopherson @ 2024-01-02 17:58 UTC (permalink / raw) To: Ben Mesman | Spark Narrowcasting Cc: Thomas Gleixner, Ingo Molnar, Borislav Petkov, Dave Hansen, x86@kernel.org, linux-kernel@vger.kernel.org, Ulf Hansson, Fred Ai, Adrian Hunter On Thu, Dec 28, 2023, Ben Mesman | Spark Narrowcasting wrote: > > Please don't send private mails. Kudos for using get_maintainer.pl, but a demerit > > for not Cc'ing the mailing lists :-) > > > > https://people.kernel.org/tglx/notes-about-netiquette > > Definitely saving that in my URLs-cache. Might need it again in a few years :-) > (last time I needed it was about 10 years ago) > > > > I recently started upgrading some of my remote managed thin-clients from a > > > 5.15.x kernel to a 6.1.x kernel. When rebooting with the new(er) kernel, the > > > HP t640 clients failed. The problem is that after the warm reboot, the BIOS > > > is unable to locate the internal storage (so it can't boot a valid OS). > > > > > > With some digging around I found that adding "reboot=p" will solve the > > > problem, but because the systems are remote managed, I am unable to add this > > > boot-parameter in any straightforward way. > [snip] > > I'm not familiar with this code (I'm not actually a maintainer/reviewer for this > > code, by default get_maintainer.pl Cc's people that have recently modified the > > file in question), but this looks like a hack to workaround a bug elsewhere. > > > > All of these quirks are obviously workarounds for some kind of bug, but AFAICT > > the quirks are to workaround hardware or firmware bugs, not kernel bugs. Since > > 5.15.x kernels worked, odds are good a bug was introduced between 5.15 and 6.1, > > i.e. that this is fudging around a kernel bug that can and should be fixed. > > > > Are you able to bisect the kernel between 6.1 and 5.15 to try and pinpoint an > > exact commit that introduced the problem? > > That took a few days, but resulted in the following: > > 4be33cf187036744b4ed84824e7157cfc09c6f4c is the first bad commit > commit 4be33cf187036744b4ed84824e7157cfc09c6f4c > Author: Fred Ai <fred.ai@bayhubtech.com> > Date: Mon Dec 20 20:09:40 2021 -0800 > > mmc: sdhci-pci-o2micro: Improve card input timing at SDR104/HS200 mode > > Card input timing is margin, need to adjust the hold timing of card input. > > Signed-off-by: Fred Ai <fred.ai@bayhubtech.com> > Link: https://lore.kernel.org/r/20211221040940.484-1-fred.ai@bayhubtech.com > Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> > > drivers/mmc/host/sdhci-pci-o2micro.c | 57 ++++++++++++++++++++++++++++++------ > 1 file changed, 48 insertions(+), 9 deletions(-) > > I'm not sure how this code impacts this device, but it does contain a "HS200 MMC card": > $ dmesg | grep mmc > [ 1.044708] mmc0: emmc 1.8v flag is set, force 1.8v signaling voltage > [ 1.044937] mmc0: SDHCI controller on PCI [0000:01:00.0] using ADMA > [ 2.120632] mmc0: new HS200 MMC card at address 0001 > [ 2.122912] mmcblk0: mmc0:0001 hA8aP> 14.7 GiB > [ 2.124810] mmcblk0: p1 p2 p3 > > I can provide more info on the hardware, which is also available in https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=1056056 Adding the relevant people from that commit, this is waaaaay outside my area of expertise. ^ permalink raw reply [flat|nested] 9+ messages in thread
* 回复: Bug: After a 'warm' reboot the disk is missing (not detected by the bios) on a HP t640 2024-01-02 17:58 ` Sean Christopherson @ 2024-01-03 12:23 ` Fred Ai(WH) 2024-01-04 10:31 ` Ben Mesman | Spark Narrowcasting 0 siblings, 1 reply; 9+ messages in thread From: Fred Ai(WH) @ 2024-01-03 12:23 UTC (permalink / raw) To: Sean Christopherson, Ben Mesman | Spark Narrowcasting Cc: Thomas Gleixner, Ingo Molnar, Borislav Petkov, Dave Hansen, x86@kernel.org, linux-kernel@vger.kernel.org, Ulf Hansson, Adrian Hunter, Chevron Li (WH), Shaper Liu (WH) [-- Attachment #1: Type: text/plain, Size: 5684 bytes --] Hi Sean Christopherson I am maintainer of module “sdhci-pci-o2micro”. I provide the attachment code to fix this issue, but I didn't test this path code. You can test attachment patch code and give the feedback to me. If this issue can be fixed by this patch, I will consider committing the new patch to fix this issue at linux master branch. Diff patch in "linux/drivers/mmc/host/sdhci-pci-o2micro.c" as below: diff --git a/sdhci-pci-o2micro.c b/sdhci-pci-o2micro.c index 620f52a..d520369 100644 --- a/sdhci-pci-o2micro.c +++ b/sdhci-pci-o2micro.c @@ -603,6 +603,31 @@ static void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock) sdhci_o2_enable_clk(host, clk); } +static void sdhci_pci_o2_remove_slot(struct sdhci_pci_slot *slot, int dead) +{ + u8 scratch_8 = 0; + u32 reg_val = 0; + struct sdhci_pci_chip *chip; + + chip = slot->chip; + + /* UnLock WP */ + pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8); + scratch_8 &= 0x7f; + pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); + + /* Set pcr 0x354[16] to switch Clock Source back to OPE Clock */ + pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, ®_val); + reg_val &= ~(O2_SD_SEL_DLL); + pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, reg_val); + + /* Lock WP */ + pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8); + scratch_8 |= 0x80; + pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); + +} + static int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot) { struct sdhci_pci_chip *chip; @@ -924,4 +949,5 @@ const struct sdhci_pci_fixes sdhci_o2 = { #endif .ops = &sdhci_pci_o2_ops, .priv_size = sizeof(struct o2_host), + .remove_slot= sdhci_pci_o2_remove_slot, }; Thanks Fred -----邮件原件----- 发件人: Sean Christopherson <seanjc@google.com> 发送时间: 2024年1月3日 1:59 收件人: Ben Mesman | Spark Narrowcasting <ben@sparknarrowcasting.nl> 抄送: Thomas Gleixner <tglx@linutronix.de>; Ingo Molnar <mingo@redhat.com>; Borislav Petkov <bp@alien8.de>; Dave Hansen <dave.hansen@linux.intel.com>; x86@kernel.org; linux-kernel@vger.kernel.org; Ulf Hansson <ulf.hansson@linaro.org>; Fred Ai(WH) <fred.ai@bayhubtech.com>; Adrian Hunter <adrian.hunter@intel.com> 主题: Re: Bug: After a 'warm' reboot the disk is missing (not detected by the bios) on a HP t640 On Thu, Dec 28, 2023, Ben Mesman | Spark Narrowcasting wrote: > > Please don't send private mails. Kudos for using get_maintainer.pl, > > but a demerit for not Cc'ing the mailing lists :-) > > > > https://people.kernel.org/tglx/notes-about-netiquette > > Definitely saving that in my URLs-cache. Might need it again in a few > years :-) (last time I needed it was about 10 years ago) > > > > I recently started upgrading some of my remote managed > > > thin-clients from a 5.15.x kernel to a 6.1.x kernel. When > > > rebooting with the new(er) kernel, the HP t640 clients failed. The > > > problem is that after the warm reboot, the BIOS is unable to locate the internal storage (so it can't boot a valid OS). > > > > > > With some digging around I found that adding "reboot=p" will solve > > > the problem, but because the systems are remote managed, I am > > > unable to add this boot-parameter in any straightforward way. > [snip] > > I'm not familiar with this code (I'm not actually a > > maintainer/reviewer for this code, by default get_maintainer.pl Cc's > > people that have recently modified the file in question), but this looks like a hack to workaround a bug elsewhere. > > > > All of these quirks are obviously workarounds for some kind of bug, > > but AFAICT the quirks are to workaround hardware or firmware bugs, > > not kernel bugs. Since 5.15.x kernels worked, odds are good a bug > > was introduced between 5.15 and 6.1, i.e. that this is fudging around a kernel bug that can and should be fixed. > > > > Are you able to bisect the kernel between 6.1 and 5.15 to try and > > pinpoint an exact commit that introduced the problem? > > That took a few days, but resulted in the following: > > 4be33cf187036744b4ed84824e7157cfc09c6f4c is the first bad commit > commit 4be33cf187036744b4ed84824e7157cfc09c6f4c > Author: Fred Ai <fred.ai@bayhubtech.com> > Date: Mon Dec 20 20:09:40 2021 -0800 > > mmc: sdhci-pci-o2micro: Improve card input timing at SDR104/HS200 > mode > > Card input timing is margin, need to adjust the hold timing of card input. > > Signed-off-by: Fred Ai <fred.ai@bayhubtech.com> > Link: https://lore.kernel.org/r/20211221040940.484-1-fred.ai@bayhubtech.com > Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> > > drivers/mmc/host/sdhci-pci-o2micro.c | 57 > ++++++++++++++++++++++++++++++------ > 1 file changed, 48 insertions(+), 9 deletions(-) > > I'm not sure how this code impacts this device, but it does contain a "HS200 MMC card": > $ dmesg | grep mmc > [ 1.044708] mmc0: emmc 1.8v flag is set, force 1.8v signaling voltage > [ 1.044937] mmc0: SDHCI controller on PCI [0000:01:00.0] using ADMA > [ 2.120632] mmc0: new HS200 MMC card at address 0001 > [ 2.122912] mmcblk0: mmc0:0001 hA8aP> 14.7 GiB > [ 2.124810] mmcblk0: p1 p2 p3 > > I can provide more info on the hardware, which is also available in > https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=1056056 Adding the relevant people from that commit, this is waaaaay outside my area of expertise. [-- Attachment #2: sdhci-pci-o2micro.c --] [-- Type: text/plain, Size: 27172 bytes --] // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2013 BayHub Technology Ltd. * * Authors: Peter Guo <peter.guo@bayhubtech.com> * Adam Lee <adam.lee@canonical.com> * Ernest Zhang <ernest.zhang@bayhubtech.com> */ #include <linux/pci.h> #include <linux/mmc/host.h> #include <linux/mmc/mmc.h> #include <linux/delay.h> #include <linux/iopoll.h> #include <linux/bitfield.h> #include "sdhci.h" #include "sdhci-pci.h" /* * O2Micro device registers */ #define O2_SD_MISC_REG5 0x64 #define O2_SD_LD0_CTRL 0x68 #define O2_SD_DEV_CTRL 0x88 #define O2_SD_LOCK_WP 0xD3 #define O2_SD_TEST_REG 0xD4 #define O2_SD_FUNC_REG0 0xDC #define O2_SD_MULTI_VCC3V 0xEE #define O2_SD_CLKREQ 0xEC #define O2_SD_CAPS 0xE0 #define O2_SD_ADMA1 0xE2 #define O2_SD_ADMA2 0xE7 #define O2_SD_MISC_CTRL2 0xF0 #define O2_SD_INF_MOD 0xF1 #define O2_SD_MISC_CTRL4 0xFC #define O2_SD_MISC_CTRL 0x1C0 #define O2_SD_PWR_FORCE_L0 0x0002 #define O2_SD_TUNING_CTRL 0x300 #define O2_SD_PLL_SETTING 0x304 #define O2_SD_MISC_SETTING 0x308 #define O2_SD_CLK_SETTING 0x328 #define O2_SD_CAP_REG2 0x330 #define O2_SD_CAP_REG0 0x334 #define O2_SD_UHS1_CAP_SETTING 0x33C #define O2_SD_DELAY_CTRL 0x350 #define O2_SD_OUTPUT_CLK_SOURCE_SWITCH 0x354 #define O2_SD_UHS2_L1_CTRL 0x35C #define O2_SD_FUNC_REG3 0x3E0 #define O2_SD_FUNC_REG4 0x3E4 #define O2_SD_LED_ENABLE BIT(6) #define O2_SD_FREG0_LEDOFF BIT(13) #define O2_SD_SEL_DLL BIT(16) #define O2_SD_FREG4_ENABLE_CLK_SET BIT(22) #define O2_SD_PHASE_MASK GENMASK(23, 20) #define O2_SD_FIX_PHASE FIELD_PREP(O2_SD_PHASE_MASK, 0x9) #define O2_SD_VENDOR_SETTING 0x110 #define O2_SD_VENDOR_SETTING2 0x1C8 #define O2_SD_HW_TUNING_DISABLE BIT(4) #define O2_PLL_DLL_WDT_CONTROL1 0x1CC #define O2_PLL_FORCE_ACTIVE BIT(18) #define O2_PLL_LOCK_STATUS BIT(14) #define O2_PLL_SOFT_RESET BIT(12) #define O2_DLL_LOCK_STATUS BIT(11) #define O2_SD_DETECT_SETTING 0x324 static const u32 dmdn_table[] = {0x2B1C0000, 0x2C1A0000, 0x371B0000, 0x35100000}; #define DMDN_SZ ARRAY_SIZE(dmdn_table) struct o2_host { u8 dll_adjust_count; }; static void sdhci_o2_wait_card_detect_stable(struct sdhci_host *host) { ktime_t timeout; u32 scratch32; /* Wait max 50 ms */ timeout = ktime_add_ms(ktime_get(), 50); while (1) { bool timedout = ktime_after(ktime_get(), timeout); scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE); if ((scratch32 & SDHCI_CARD_PRESENT) >> SDHCI_CARD_PRES_SHIFT == (scratch32 & SDHCI_CD_LVL) >> SDHCI_CD_LVL_SHIFT) break; if (timedout) { pr_err("%s: Card Detect debounce never finished.\n", mmc_hostname(host->mmc)); sdhci_dumpregs(host); return; } udelay(10); } } static void sdhci_o2_enable_internal_clock(struct sdhci_host *host) { ktime_t timeout; u16 scratch; u32 scratch32; /* PLL software reset */ scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); scratch32 |= O2_PLL_SOFT_RESET; sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); udelay(1); scratch32 &= ~(O2_PLL_SOFT_RESET); sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); /* PLL force active */ scratch32 |= O2_PLL_FORCE_ACTIVE; sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); /* Wait max 20 ms */ timeout = ktime_add_ms(ktime_get(), 20); while (1) { bool timedout = ktime_after(ktime_get(), timeout); scratch = sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1); if (scratch & O2_PLL_LOCK_STATUS) break; if (timedout) { pr_err("%s: Internal clock never stabilised.\n", mmc_hostname(host->mmc)); sdhci_dumpregs(host); goto out; } udelay(10); } /* Wait for card detect finish */ udelay(1); sdhci_o2_wait_card_detect_stable(host); out: /* Cancel PLL force active */ scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); scratch32 &= ~O2_PLL_FORCE_ACTIVE; sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); } static int sdhci_o2_get_cd(struct mmc_host *mmc) { struct sdhci_host *host = mmc_priv(mmc); if (!(sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1) & O2_PLL_LOCK_STATUS)) sdhci_o2_enable_internal_clock(host); else sdhci_o2_wait_card_detect_stable(host); return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); } static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value) { u32 scratch_32; pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32); scratch_32 &= 0x0000FFFF; scratch_32 |= value; pci_write_config_dword(chip->pdev, O2_SD_PLL_SETTING, scratch_32); } static u32 sdhci_o2_pll_dll_wdt_control(struct sdhci_host *host) { return sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); } /* * This function is used to detect dll lock status. * Since the dll lock status bit will toggle randomly * with very short interval which needs to be polled * as fast as possible. Set sleep_us as 1 microsecond. */ static int sdhci_o2_wait_dll_detect_lock(struct sdhci_host *host) { u32 scratch32 = 0; return readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host, scratch32, !(scratch32 & O2_DLL_LOCK_STATUS), 1, 1000000); } static void sdhci_o2_set_tuning_mode(struct sdhci_host *host) { u16 reg; /* enable hardware tuning */ reg = sdhci_readw(host, O2_SD_VENDOR_SETTING); reg &= ~O2_SD_HW_TUNING_DISABLE; sdhci_writew(host, reg, O2_SD_VENDOR_SETTING); } static void __sdhci_o2_execute_tuning(struct sdhci_host *host, u32 opcode) { int i; sdhci_send_tuning(host, opcode); for (i = 0; i < 150; i++) { u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) { if (ctrl & SDHCI_CTRL_TUNED_CLK) { host->tuning_done = true; return; } pr_warn("%s: HW tuning failed !\n", mmc_hostname(host->mmc)); break; } mdelay(1); } pr_info("%s: Tuning failed, falling back to fixed sampling clock\n", mmc_hostname(host->mmc)); sdhci_reset_tuning(host); } /* * This function is used to fix o2 dll shift issue. * It isn't necessary to detect card present before recovery. * Firstly, it is used by bht emmc card, which is embedded. * Second, before call recovery card present will be detected * outside of the execute tuning function. */ static int sdhci_o2_dll_recovery(struct sdhci_host *host) { int ret = 0; u8 scratch_8 = 0; u32 scratch_32 = 0; struct sdhci_pci_slot *slot = sdhci_priv(host); struct sdhci_pci_chip *chip = slot->chip; struct o2_host *o2_host = sdhci_pci_priv(slot); /* UnLock WP */ pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8); scratch_8 &= 0x7f; pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); while (o2_host->dll_adjust_count < DMDN_SZ && !ret) { /* Disable clock */ sdhci_writeb(host, 0, SDHCI_CLOCK_CONTROL); /* PLL software reset */ scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); scratch_32 |= O2_PLL_SOFT_RESET; sdhci_writel(host, scratch_32, O2_PLL_DLL_WDT_CONTROL1); pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG4, &scratch_32); /* Enable Base Clk setting change */ scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET; pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG4, scratch_32); o2_pci_set_baseclk(chip, dmdn_table[o2_host->dll_adjust_count]); /* Enable internal clock */ scratch_8 = SDHCI_CLOCK_INT_EN; sdhci_writeb(host, scratch_8, SDHCI_CLOCK_CONTROL); if (sdhci_o2_get_cd(host->mmc)) { /* * need wait at least 5ms for dll status stable, * after enable internal clock */ usleep_range(5000, 6000); if (sdhci_o2_wait_dll_detect_lock(host)) { scratch_8 |= SDHCI_CLOCK_CARD_EN; sdhci_writeb(host, scratch_8, SDHCI_CLOCK_CONTROL); ret = 1; } else { pr_warn("%s: DLL unlocked when dll_adjust_count is %d.\n", mmc_hostname(host->mmc), o2_host->dll_adjust_count); } } else { pr_err("%s: card present detect failed.\n", mmc_hostname(host->mmc)); break; } o2_host->dll_adjust_count++; } if (!ret && o2_host->dll_adjust_count == DMDN_SZ) pr_err("%s: DLL adjust over max times\n", mmc_hostname(host->mmc)); /* Lock WP */ pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8); scratch_8 |= 0x80; pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); return ret; } static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode) { struct sdhci_host *host = mmc_priv(mmc); struct sdhci_pci_slot *slot = sdhci_priv(host); struct sdhci_pci_chip *chip = slot->chip; int current_bus_width = 0; u32 scratch32 = 0; u16 scratch = 0; u8 scratch_8 = 0; u32 reg_val; /* * This handler implements the hardware tuning that is specific to * this controller. Fall back to the standard method for other TIMING. */ if ((host->timing != MMC_TIMING_MMC_HS200) && (host->timing != MMC_TIMING_UHS_SDR104) && (host->timing != MMC_TIMING_UHS_SDR50)) return sdhci_execute_tuning(mmc, opcode); if (WARN_ON(!mmc_op_tuning(opcode))) return -EINVAL; /* Force power mode enter L0 */ scratch = sdhci_readw(host, O2_SD_MISC_CTRL); scratch |= O2_SD_PWR_FORCE_L0; sdhci_writew(host, scratch, O2_SD_MISC_CTRL); /* Stop clk */ reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL); reg_val &= ~SDHCI_CLOCK_CARD_EN; sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL); if ((host->timing == MMC_TIMING_MMC_HS200) || (host->timing == MMC_TIMING_UHS_SDR104)) { /* UnLock WP */ pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8); scratch_8 &= 0x7f; pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); /* Set pcr 0x354[16] to choose dll clock, and set the default phase */ pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, ®_val); reg_val &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK); reg_val |= (O2_SD_SEL_DLL | O2_SD_FIX_PHASE); pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, reg_val); /* Lock WP */ pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8); scratch_8 |= 0x80; pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); } /* Start clk */ reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL); reg_val |= SDHCI_CLOCK_CARD_EN; sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL); /* wait DLL lock, timeout value 5ms */ if (readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host, scratch32, (scratch32 & O2_DLL_LOCK_STATUS), 1, 5000)) pr_warn("%s: DLL can't lock in 5ms after force L0 during tuning.\n", mmc_hostname(host->mmc)); /* * Judge the tuning reason, whether caused by dll shift * If cause by dll shift, should call sdhci_o2_dll_recovery */ if (!sdhci_o2_wait_dll_detect_lock(host)) if (!sdhci_o2_dll_recovery(host)) { pr_err("%s: o2 dll recovery failed\n", mmc_hostname(host->mmc)); return -EINVAL; } /* * o2 sdhci host didn't support 8bit emmc tuning */ if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) { current_bus_width = mmc->ios.bus_width; mmc->ios.bus_width = MMC_BUS_WIDTH_4; sdhci_set_bus_width(host, MMC_BUS_WIDTH_4); } sdhci_o2_set_tuning_mode(host); sdhci_start_tuning(host); __sdhci_o2_execute_tuning(host, opcode); sdhci_end_tuning(host); if (current_bus_width == MMC_BUS_WIDTH_8) { mmc->ios.bus_width = MMC_BUS_WIDTH_8; sdhci_set_bus_width(host, current_bus_width); } /* Cancel force power mode enter L0 */ scratch = sdhci_readw(host, O2_SD_MISC_CTRL); scratch &= ~(O2_SD_PWR_FORCE_L0); sdhci_writew(host, scratch, O2_SD_MISC_CTRL); sdhci_reset(host, SDHCI_RESET_CMD); sdhci_reset(host, SDHCI_RESET_DATA); host->flags &= ~SDHCI_HS400_TUNING; return 0; } static void o2_pci_led_enable(struct sdhci_pci_chip *chip) { int ret; u32 scratch_32; /* Set led of SD host function enable */ ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG0, &scratch_32); if (ret) return; scratch_32 &= ~O2_SD_FREG0_LEDOFF; pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG0, scratch_32); ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32); if (ret) return; scratch_32 |= O2_SD_LED_ENABLE; pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32); } static void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip) { u32 scratch_32; int ret; /* Improve write performance for SD3.0 */ ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32); if (ret) return; scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14)); pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32); /* Enable Link abnormal reset generating Reset */ ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32); if (ret) return; scratch_32 &= ~((1 << 19) | (1 << 11)); scratch_32 |= (1 << 10); pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32); /* set card power over current protection */ ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32); if (ret) return; scratch_32 |= (1 << 4); pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32); /* adjust the output delay for SD mode */ pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492); /* Set the output voltage setting of Aux 1.2v LDO */ ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32); if (ret) return; scratch_32 &= ~(3 << 12); pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32); /* Set Max power supply capability of SD host */ ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32); if (ret) return; scratch_32 &= ~(0x01FE); scratch_32 |= 0x00CC; pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32); /* Set DLL Tuning Window */ ret = pci_read_config_dword(chip->pdev, O2_SD_TUNING_CTRL, &scratch_32); if (ret) return; scratch_32 &= ~(0x000000FF); scratch_32 |= 0x00000066; pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32); /* Set UHS2 T_EIDLE */ ret = pci_read_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, &scratch_32); if (ret) return; scratch_32 &= ~(0x000000FC); scratch_32 |= 0x00000084; pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32); /* Set UHS2 Termination */ ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32); if (ret) return; scratch_32 &= ~((1 << 21) | (1 << 30)); pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32); /* Set L1 Entrance Timer */ ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32); if (ret) return; scratch_32 &= ~(0xf0000000); scratch_32 |= 0x30000000; pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32); ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_CTRL4, &scratch_32); if (ret) return; scratch_32 &= ~(0x000f0000); scratch_32 |= 0x00080000; pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32); } static void sdhci_pci_o2_enable_msi(struct sdhci_pci_chip *chip, struct sdhci_host *host) { int ret; ret = pci_find_capability(chip->pdev, PCI_CAP_ID_MSI); if (!ret) { pr_info("%s: unsupported MSI, use INTx irq\n", mmc_hostname(host->mmc)); return; } ret = pci_alloc_irq_vectors(chip->pdev, 1, 1, PCI_IRQ_MSI | PCI_IRQ_MSIX); if (ret < 0) { pr_err("%s: enable PCI MSI failed, err=%d\n", mmc_hostname(host->mmc), ret); return; } host->irq = pci_irq_vector(chip->pdev, 0); } static void sdhci_o2_enable_clk(struct sdhci_host *host, u16 clk) { /* Enable internal clock */ clk |= SDHCI_CLOCK_INT_EN; sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); sdhci_o2_enable_internal_clock(host); if (sdhci_o2_get_cd(host->mmc)) { clk |= SDHCI_CLOCK_CARD_EN; sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); } } static void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock) { u16 clk; u8 scratch; u32 scratch_32; struct sdhci_pci_slot *slot = sdhci_priv(host); struct sdhci_pci_chip *chip = slot->chip; host->mmc->actual_clock = 0; sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); if (clock == 0) return; /* UnLock WP */ pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); scratch &= 0x7f; pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); if ((host->timing == MMC_TIMING_UHS_SDR104) && (clock == 200000000)) { pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32); if ((scratch_32 & 0xFFFF0000) != 0x2c280000) o2_pci_set_baseclk(chip, 0x2c280000); } else { pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32); if ((scratch_32 & 0xFFFF0000) != 0x25100000) o2_pci_set_baseclk(chip, 0x25100000); } pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &scratch_32); scratch_32 &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK); pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, scratch_32); /* Lock WP */ pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); scratch |= 0x80; pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); sdhci_o2_enable_clk(host, clk); } static void sdhci_pci_o2_remove_slot(struct sdhci_pci_slot *slot, int dead) { u8 scratch_8 = 0; u32 reg_val = 0; struct sdhci_pci_chip *chip; chip = slot->chip; /* UnLock WP */ pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8); scratch_8 &= 0x7f; pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); /* Set pcr 0x354[16] to switch Clock Source back to OPE Clock */ pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, ®_val); reg_val &= ~(O2_SD_SEL_DLL); pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, reg_val); /* Lock WP */ pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8); scratch_8 |= 0x80; pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); } static int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot) { struct sdhci_pci_chip *chip; struct sdhci_host *host; struct o2_host *o2_host = sdhci_pci_priv(slot); u32 reg, caps; int ret; chip = slot->chip; host = slot->host; o2_host->dll_adjust_count = 0; caps = sdhci_readl(host, SDHCI_CAPABILITIES); /* * mmc_select_bus_width() will test the bus to determine the actual bus * width. */ if (caps & SDHCI_CAN_DO_8BIT) host->mmc->caps |= MMC_CAP_8_BIT_DATA; switch (chip->pdev->device) { case PCI_DEVICE_ID_O2_SDS0: case PCI_DEVICE_ID_O2_SEABIRD0: case PCI_DEVICE_ID_O2_SEABIRD1: case PCI_DEVICE_ID_O2_SDS1: case PCI_DEVICE_ID_O2_FUJIN2: reg = sdhci_readl(host, O2_SD_VENDOR_SETTING); if (reg & 0x1) host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12; host->quirks2 |= SDHCI_QUIRK2_BROKEN_DDR50; sdhci_pci_o2_enable_msi(chip, host); if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD0) { ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_SETTING, ®); if (ret) return -EIO; if (reg & (1 << 4)) { pr_info("%s: emmc 1.8v flag is set, force 1.8v signaling voltage\n", mmc_hostname(host->mmc)); host->flags &= ~SDHCI_SIGNALING_330; host->flags |= SDHCI_SIGNALING_180; host->mmc->caps2 |= MMC_CAP2_NO_SD; host->mmc->caps2 |= MMC_CAP2_NO_SDIO; pci_write_config_dword(chip->pdev, O2_SD_DETECT_SETTING, 3); } slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd; } if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD1) { slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd; host->mmc->caps2 |= MMC_CAP2_NO_SDIO; host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; } host->mmc_host_ops.execute_tuning = sdhci_o2_execute_tuning; if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2) break; /* set dll watch dog timer */ reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2); reg |= (1 << 12); sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2); break; default: break; } return 0; } static int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip) { int ret; u8 scratch; u32 scratch_32; switch (chip->pdev->device) { case PCI_DEVICE_ID_O2_8220: case PCI_DEVICE_ID_O2_8221: case PCI_DEVICE_ID_O2_8320: case PCI_DEVICE_ID_O2_8321: /* This extra setup is required due to broken ADMA. */ ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); if (ret) return ret; scratch &= 0x7f; pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); /* Set Multi 3 to VCC3V# */ pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08); /* Disable CLK_REQ# support after media DET */ ret = pci_read_config_byte(chip->pdev, O2_SD_CLKREQ, &scratch); if (ret) return ret; scratch |= 0x20; pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch); /* Choose capabilities, enable SDMA. We have to write 0x01 * to the capabilities register first to unlock it. */ ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch); if (ret) return ret; scratch |= 0x01; pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch); pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73); /* Disable ADMA1/2 */ pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39); pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08); /* Disable the infinite transfer mode */ ret = pci_read_config_byte(chip->pdev, O2_SD_INF_MOD, &scratch); if (ret) return ret; scratch |= 0x08; pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch); /* Lock WP */ ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); if (ret) return ret; scratch |= 0x80; pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); break; case PCI_DEVICE_ID_O2_SDS0: case PCI_DEVICE_ID_O2_SDS1: case PCI_DEVICE_ID_O2_FUJIN2: /* UnLock WP */ ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); if (ret) return ret; scratch &= 0x7f; pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); /* DevId=8520 subId= 0x11 or 0x12 Type Chip support */ if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) { ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG0, &scratch_32); if (ret) return ret; scratch_32 = ((scratch_32 & 0xFF000000) >> 24); /* Check Whether subId is 0x11 or 0x12 */ if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) { scratch_32 = 0x25100000; o2_pci_set_baseclk(chip, scratch_32); ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG4, &scratch_32); if (ret) return ret; /* Enable Base Clk setting change */ scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET; pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG4, scratch_32); /* Set Tuning Window to 4 */ pci_write_config_byte(chip->pdev, O2_SD_TUNING_CTRL, 0x44); break; } } /* Enable 8520 led function */ o2_pci_led_enable(chip); /* Set timeout CLK */ ret = pci_read_config_dword(chip->pdev, O2_SD_CLK_SETTING, &scratch_32); if (ret) return ret; scratch_32 &= ~(0xFF00); scratch_32 |= 0x07E0C800; pci_write_config_dword(chip->pdev, O2_SD_CLK_SETTING, scratch_32); ret = pci_read_config_dword(chip->pdev, O2_SD_CLKREQ, &scratch_32); if (ret) return ret; scratch_32 |= 0x3; pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32); ret = pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32); if (ret) return ret; scratch_32 &= ~(0x1F3F070E); scratch_32 |= 0x18270106; pci_write_config_dword(chip->pdev, O2_SD_PLL_SETTING, scratch_32); /* Disable UHS1 funciton */ ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG2, &scratch_32); if (ret) return ret; scratch_32 &= ~(0xE0); pci_write_config_dword(chip->pdev, O2_SD_CAP_REG2, scratch_32); if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) sdhci_pci_o2_fujin2_pci_init(chip); /* Lock WP */ ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); if (ret) return ret; scratch |= 0x80; pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); break; case PCI_DEVICE_ID_O2_SEABIRD0: case PCI_DEVICE_ID_O2_SEABIRD1: /* UnLock WP */ ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); if (ret) return ret; scratch &= 0x7f; pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); ret = pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32); if (ret) return ret; if ((scratch_32 & 0xff000000) == 0x01000000) { scratch_32 &= 0x0000FFFF; scratch_32 |= 0x1F340000; pci_write_config_dword(chip->pdev, O2_SD_PLL_SETTING, scratch_32); } else { scratch_32 &= 0x0000FFFF; scratch_32 |= 0x25100000; pci_write_config_dword(chip->pdev, O2_SD_PLL_SETTING, scratch_32); ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG4, &scratch_32); if (ret) return ret; scratch_32 |= (1 << 22); pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG4, scratch_32); } /* Set Tuning Windows to 5 */ pci_write_config_byte(chip->pdev, O2_SD_TUNING_CTRL, 0x55); //Adjust 1st and 2nd CD debounce time pci_read_config_dword(chip->pdev, O2_SD_MISC_CTRL2, &scratch_32); scratch_32 &= 0xFFE7FFFF; scratch_32 |= 0x00180000; pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL2, scratch_32); pci_write_config_dword(chip->pdev, O2_SD_DETECT_SETTING, 1); /* Lock WP */ ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); if (ret) return ret; scratch |= 0x80; pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); break; } return 0; } #ifdef CONFIG_PM_SLEEP static int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip) { sdhci_pci_o2_probe(chip); return sdhci_pci_resume_host(chip); } #endif static const struct sdhci_ops sdhci_pci_o2_ops = { .set_clock = sdhci_pci_o2_set_clock, .enable_dma = sdhci_pci_enable_dma, .set_bus_width = sdhci_set_bus_width, .reset = sdhci_reset, .set_uhs_signaling = sdhci_set_uhs_signaling, }; const struct sdhci_pci_fixes sdhci_o2 = { .probe = sdhci_pci_o2_probe, .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD, .probe_slot = sdhci_pci_o2_probe_slot, #ifdef CONFIG_PM_SLEEP .resume = sdhci_pci_o2_resume, #endif .ops = &sdhci_pci_o2_ops, .priv_size = sizeof(struct o2_host), .remove_slot= sdhci_pci_o2_remove_slot, }; ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: Bug: After a 'warm' reboot the disk is missing (not detected by the bios) on a HP t640 2024-01-03 12:23 ` 回复: " Fred Ai(WH) @ 2024-01-04 10:31 ` Ben Mesman | Spark Narrowcasting 2024-01-08 2:02 ` 回复: " Fred Ai(WH) 0 siblings, 1 reply; 9+ messages in thread From: Ben Mesman | Spark Narrowcasting @ 2024-01-04 10:31 UTC (permalink / raw) To: Fred Ai(WH), Sean Christopherson Cc: Thomas Gleixner, Ingo Molnar, Borislav Petkov, Dave Hansen, x86@kernel.org, linux-kernel@vger.kernel.org, Ulf Hansson, Adrian Hunter, Chevron Li (WH), Shaper Liu (WH) Hi Fred Ai, > Hi Sean Christopherson > I am maintainer of module “sdhci-pci-o2micro”. I provide the attachment code to fix this issue, but I didn't test this path code. You can test attachment patch code and give the feedback to me. > If this issue can be fixed by this patch, I will consider committing the new patch to fix this issue at linux master branch. I tried the patch, but it didn't solve the issue, sorry. Do you need any extra info? Any other help I can give to solve this problem? Thanks, Ben Mesman. -- > Diff patch in "linux/drivers/mmc/host/sdhci-pci-o2micro.c" as below: > > diff --git a/sdhci-pci-o2micro.c b/sdhci-pci-o2micro.c > index 620f52a..d520369 100644 > --- a/sdhci-pci-o2micro.c > +++ b/sdhci-pci-o2micro.c > @@ -603,6 +603,31 @@ static void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock) > sdhci_o2_enable_clk(host, clk); > } > > +static void sdhci_pci_o2_remove_slot(struct sdhci_pci_slot *slot, int dead) > +{ > + u8 scratch_8 = 0; > + u32 reg_val = 0; > + struct sdhci_pci_chip *chip; > + > + chip = slot->chip; > + > + /* UnLock WP */ > + pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8); > + scratch_8 &= 0x7f; > + pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); > + > + /* Set pcr 0x354[16] to switch Clock Source back to OPE Clock */ > + pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, ®_val); > + reg_val &= ~(O2_SD_SEL_DLL); > + pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, reg_val); > + > + /* Lock WP */ > + pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8); > + scratch_8 |= 0x80; > + pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); > + > +} > + > static int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot) > { > struct sdhci_pci_chip *chip; > @@ -924,4 +949,5 @@ const struct sdhci_pci_fixes sdhci_o2 = { > #endif > .ops = &sdhci_pci_o2_ops, > .priv_size = sizeof(struct o2_host), > + .remove_slot= sdhci_pci_o2_remove_slot, > }; > > > Thanks > Fred ^ permalink raw reply [flat|nested] 9+ messages in thread
* 回复: Bug: After a 'warm' reboot the disk is missing (not detected by the bios) on a HP t640 2024-01-04 10:31 ` Ben Mesman | Spark Narrowcasting @ 2024-01-08 2:02 ` Fred Ai(WH) 2024-01-09 12:25 ` Ben Mesman | Spark Narrowcasting 0 siblings, 1 reply; 9+ messages in thread From: Fred Ai(WH) @ 2024-01-08 2:02 UTC (permalink / raw) To: Ben Mesman | Spark Narrowcasting, Sean Christopherson Cc: Thomas Gleixner, Ingo Molnar, Borislav Petkov, Dave Hansen, x86@kernel.org, linux-kernel@vger.kernel.org, Ulf Hansson, Adrian Hunter, Chevron Li (WH), Shaper Liu (WH) Hi Ben Mesman, > I tried the patch, but it didn't solve the issue, sorry. > Do you need any extra info? Any other help I can give to solve this problem? Please make sure you compile in a way that allows our patch to take effect, or you can add debugging information to ensure that our patch works. Thanks Fred -----邮件原件----- 发件人: Ben Mesman | Spark Narrowcasting <ben@sparknarrowcasting.nl> 发送时间: 2024年1月4日 18:31 收件人: Fred Ai(WH) <fred.ai@bayhubtech.com>; Sean Christopherson <seanjc@google.com> 抄送: Thomas Gleixner <tglx@linutronix.de>; Ingo Molnar <mingo@redhat.com>; Borislav Petkov <bp@alien8.de>; Dave Hansen <dave.hansen@linux.intel.com>; x86@kernel.org; linux-kernel@vger.kernel.org; Ulf Hansson <ulf.hansson@linaro.org>; Adrian Hunter <adrian.hunter@intel.com>; Chevron Li (WH) <chevron.li@bayhubtech.com>; Shaper Liu (WH) <shaper.liu@bayhubtech.com> 主题: Re: Bug: After a 'warm' reboot the disk is missing (not detected by the bios) on a HP t640 Hi Fred Ai, > Hi Sean Christopherson > I am maintainer of module “sdhci-pci-o2micro”. I provide the attachment code to fix this issue, but I didn't test this path code. You can test attachment patch code and give the feedback to me. > If this issue can be fixed by this patch, I will consider committing the new patch to fix this issue at linux master branch. I tried the patch, but it didn't solve the issue, sorry. Do you need any extra info? Any other help I can give to solve this problem? Thanks, Ben Mesman. -- > Diff patch in "linux/drivers/mmc/host/sdhci-pci-o2micro.c" as below: > > diff --git a/sdhci-pci-o2micro.c b/sdhci-pci-o2micro.c index > 620f52a..d520369 100644 > --- a/sdhci-pci-o2micro.c > +++ b/sdhci-pci-o2micro.c > @@ -603,6 +603,31 @@ static void sdhci_pci_o2_set_clock(struct > sdhci_host *host, unsigned int clock) > sdhci_o2_enable_clk(host, clk); > } > > +static void sdhci_pci_o2_remove_slot(struct sdhci_pci_slot *slot, int > +dead) { > + u8 scratch_8 = 0; > + u32 reg_val = 0; > + struct sdhci_pci_chip *chip; > + > + chip = slot->chip; > + > + /* UnLock WP */ > + pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8); > + scratch_8 &= 0x7f; > + pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); > + > + /* Set pcr 0x354[16] to switch Clock Source back to OPE Clock > +*/ > + pci_read_config_dword(chip->pdev, > +O2_SD_OUTPUT_CLK_SOURCE_SWITCH, ®_val); > + reg_val &= ~(O2_SD_SEL_DLL); > + pci_write_config_dword(chip->pdev, > +O2_SD_OUTPUT_CLK_SOURCE_SWITCH, reg_val); > + > + /* Lock WP */ > + pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8); > + scratch_8 |= 0x80; > + pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); > + > +} > + > static int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot) > { > struct sdhci_pci_chip *chip; > @@ -924,4 +949,5 @@ const struct sdhci_pci_fixes sdhci_o2 = { > #endif > .ops = &sdhci_pci_o2_ops, > .priv_size = sizeof(struct o2_host), > + .remove_slot= sdhci_pci_o2_remove_slot, > }; > > > Thanks > Fred ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: Bug: After a 'warm' reboot the disk is missing (not detected by the bios) on a HP t640 2024-01-08 2:02 ` 回复: " Fred Ai(WH) @ 2024-01-09 12:25 ` Ben Mesman | Spark Narrowcasting 2024-01-19 8:40 ` 回复: " Fred Ai(WH) 0 siblings, 1 reply; 9+ messages in thread From: Ben Mesman | Spark Narrowcasting @ 2024-01-09 12:25 UTC (permalink / raw) To: Fred Ai(WH), Sean Christopherson Cc: Thomas Gleixner, Ingo Molnar, Borislav Petkov, Dave Hansen, x86@kernel.org, linux-kernel@vger.kernel.org, Ulf Hansson, Adrian Hunter, Chevron Li (WH), Shaper Liu (WH) Hi Fred, > Hi Ben Mesman, > > > I tried the patch, but it didn't solve the issue, sorry. > > > Do you need any extra info? Any other help I can give to solve this problem? > > Please make sure you compile in a way that allows our patch to take effect, or you can add debugging information to ensure that our patch works. I did a checkout (v6.1.70) and a compile (with the .config from debian) to check for the 'bad' situation. Then I did a 'make clean', patched the tree and did a new compile. I think that should have activated the patch. Maybe the extra .remove_slot function is not executed (or only applicable for a newer kernel version?), but I don't know how to add debugging info, sorry. Thanks, Ben Mesman. ^ permalink raw reply [flat|nested] 9+ messages in thread
* 回复: Bug: After a 'warm' reboot the disk is missing (not detected by the bios) on a HP t640 2024-01-09 12:25 ` Ben Mesman | Spark Narrowcasting @ 2024-01-19 8:40 ` Fred Ai(WH) 2024-01-22 15:52 ` Ben Mesman | Spark Narrowcasting 0 siblings, 1 reply; 9+ messages in thread From: Fred Ai(WH) @ 2024-01-19 8:40 UTC (permalink / raw) To: Ben Mesman | Spark Narrowcasting, Sean Christopherson Cc: Thomas Gleixner, Ingo Molnar, Borislav Petkov, Dave Hansen, x86@kernel.org, linux-kernel@vger.kernel.org, Ulf Hansson, Adrian Hunter, Chevron Li (WH), Shaper Liu (WH) [-- Attachment #1: Type: text/plain, Size: 1680 bytes --] Hi Ben Mesman, I changed the code by using "set_power" to recover clock source when power off card and provide the attachment code try to fix this issue, but I didn't test this path code. You can test attachment patch code and give the feedback to me. BR, Fred -----邮件原件----- 发件人: Ben Mesman | Spark Narrowcasting <ben@sparknarrowcasting.nl> 发送时间: 2024年1月9日 20:26 收件人: Fred Ai(WH) <fred.ai@bayhubtech.com>; Sean Christopherson <seanjc@google.com> 抄送: Thomas Gleixner <tglx@linutronix.de>; Ingo Molnar <mingo@redhat.com>; Borislav Petkov <bp@alien8.de>; Dave Hansen <dave.hansen@linux.intel.com>; x86@kernel.org; linux-kernel@vger.kernel.org; Ulf Hansson <ulf.hansson@linaro.org>; Adrian Hunter <adrian.hunter@intel.com>; Chevron Li (WH) <chevron.li@bayhubtech.com>; Shaper Liu (WH) <shaper.liu@bayhubtech.com> 主题: Re: Bug: After a 'warm' reboot the disk is missing (not detected by the bios) on a HP t640 Hi Fred, > Hi Ben Mesman, > > > I tried the patch, but it didn't solve the issue, sorry. > > > Do you need any extra info? Any other help I can give to solve this problem? > > Please make sure you compile in a way that allows our patch to take effect, or you can add debugging information to ensure that our patch works. I did a checkout (v6.1.70) and a compile (with the .config from debian) to check for the 'bad' situation. Then I did a 'make clean', patched the tree and did a new compile. I think that should have activated the patch. Maybe the extra .remove_slot function is not executed (or only applicable for a newer kernel version?), but I don't know how to add debugging info, sorry. Thanks, Ben Mesman. [-- Attachment #2: sdhci-pci-o2micro.c --] [-- Type: text/plain, Size: 27357 bytes --] // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2013 BayHub Technology Ltd. * * Authors: Peter Guo <peter.guo@bayhubtech.com> * Adam Lee <adam.lee@canonical.com> * Ernest Zhang <ernest.zhang@bayhubtech.com> */ #include <linux/pci.h> #include <linux/mmc/host.h> #include <linux/mmc/mmc.h> #include <linux/delay.h> #include <linux/iopoll.h> #include <linux/bitfield.h> #include "sdhci.h" #include "sdhci-pci.h" /* * O2Micro device registers */ #define O2_SD_MISC_REG5 0x64 #define O2_SD_LD0_CTRL 0x68 #define O2_SD_DEV_CTRL 0x88 #define O2_SD_LOCK_WP 0xD3 #define O2_SD_TEST_REG 0xD4 #define O2_SD_FUNC_REG0 0xDC #define O2_SD_MULTI_VCC3V 0xEE #define O2_SD_CLKREQ 0xEC #define O2_SD_CAPS 0xE0 #define O2_SD_ADMA1 0xE2 #define O2_SD_ADMA2 0xE7 #define O2_SD_MISC_CTRL2 0xF0 #define O2_SD_INF_MOD 0xF1 #define O2_SD_MISC_CTRL4 0xFC #define O2_SD_MISC_CTRL 0x1C0 #define O2_SD_PWR_FORCE_L0 0x0002 #define O2_SD_TUNING_CTRL 0x300 #define O2_SD_PLL_SETTING 0x304 #define O2_SD_MISC_SETTING 0x308 #define O2_SD_CLK_SETTING 0x328 #define O2_SD_CAP_REG2 0x330 #define O2_SD_CAP_REG0 0x334 #define O2_SD_UHS1_CAP_SETTING 0x33C #define O2_SD_DELAY_CTRL 0x350 #define O2_SD_OUTPUT_CLK_SOURCE_SWITCH 0x354 #define O2_SD_UHS2_L1_CTRL 0x35C #define O2_SD_FUNC_REG3 0x3E0 #define O2_SD_FUNC_REG4 0x3E4 #define O2_SD_LED_ENABLE BIT(6) #define O2_SD_FREG0_LEDOFF BIT(13) #define O2_SD_SEL_DLL BIT(16) #define O2_SD_FREG4_ENABLE_CLK_SET BIT(22) #define O2_SD_PHASE_MASK GENMASK(23, 20) #define O2_SD_FIX_PHASE FIELD_PREP(O2_SD_PHASE_MASK, 0x9) #define O2_SD_VENDOR_SETTING 0x110 #define O2_SD_VENDOR_SETTING2 0x1C8 #define O2_SD_HW_TUNING_DISABLE BIT(4) #define O2_PLL_DLL_WDT_CONTROL1 0x1CC #define O2_PLL_FORCE_ACTIVE BIT(18) #define O2_PLL_LOCK_STATUS BIT(14) #define O2_PLL_SOFT_RESET BIT(12) #define O2_DLL_LOCK_STATUS BIT(11) #define O2_SD_DETECT_SETTING 0x324 static const u32 dmdn_table[] = {0x2B1C0000, 0x2C1A0000, 0x371B0000, 0x35100000}; #define DMDN_SZ ARRAY_SIZE(dmdn_table) struct o2_host { u8 dll_adjust_count; }; static void sdhci_o2_wait_card_detect_stable(struct sdhci_host *host) { ktime_t timeout; u32 scratch32; /* Wait max 50 ms */ timeout = ktime_add_ms(ktime_get(), 50); while (1) { bool timedout = ktime_after(ktime_get(), timeout); scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE); if ((scratch32 & SDHCI_CARD_PRESENT) >> SDHCI_CARD_PRES_SHIFT == (scratch32 & SDHCI_CD_LVL) >> SDHCI_CD_LVL_SHIFT) break; if (timedout) { pr_err("%s: Card Detect debounce never finished.\n", mmc_hostname(host->mmc)); sdhci_dumpregs(host); return; } udelay(10); } } static void sdhci_o2_enable_internal_clock(struct sdhci_host *host) { ktime_t timeout; u16 scratch; u32 scratch32; /* PLL software reset */ scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); scratch32 |= O2_PLL_SOFT_RESET; sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); udelay(1); scratch32 &= ~(O2_PLL_SOFT_RESET); sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); /* PLL force active */ scratch32 |= O2_PLL_FORCE_ACTIVE; sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); /* Wait max 20 ms */ timeout = ktime_add_ms(ktime_get(), 20); while (1) { bool timedout = ktime_after(ktime_get(), timeout); scratch = sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1); if (scratch & O2_PLL_LOCK_STATUS) break; if (timedout) { pr_err("%s: Internal clock never stabilised.\n", mmc_hostname(host->mmc)); sdhci_dumpregs(host); goto out; } udelay(10); } /* Wait for card detect finish */ udelay(1); sdhci_o2_wait_card_detect_stable(host); out: /* Cancel PLL force active */ scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); scratch32 &= ~O2_PLL_FORCE_ACTIVE; sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); } static int sdhci_o2_get_cd(struct mmc_host *mmc) { struct sdhci_host *host = mmc_priv(mmc); if (!(sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1) & O2_PLL_LOCK_STATUS)) sdhci_o2_enable_internal_clock(host); else sdhci_o2_wait_card_detect_stable(host); return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); } static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value) { u32 scratch_32; pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32); scratch_32 &= 0x0000FFFF; scratch_32 |= value; pci_write_config_dword(chip->pdev, O2_SD_PLL_SETTING, scratch_32); } static u32 sdhci_o2_pll_dll_wdt_control(struct sdhci_host *host) { return sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); } /* * This function is used to detect dll lock status. * Since the dll lock status bit will toggle randomly * with very short interval which needs to be polled * as fast as possible. Set sleep_us as 1 microsecond. */ static int sdhci_o2_wait_dll_detect_lock(struct sdhci_host *host) { u32 scratch32 = 0; return readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host, scratch32, !(scratch32 & O2_DLL_LOCK_STATUS), 1, 1000000); } static void sdhci_o2_set_tuning_mode(struct sdhci_host *host) { u16 reg; /* enable hardware tuning */ reg = sdhci_readw(host, O2_SD_VENDOR_SETTING); reg &= ~O2_SD_HW_TUNING_DISABLE; sdhci_writew(host, reg, O2_SD_VENDOR_SETTING); } static void __sdhci_o2_execute_tuning(struct sdhci_host *host, u32 opcode) { int i; sdhci_send_tuning(host, opcode); for (i = 0; i < 150; i++) { u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) { if (ctrl & SDHCI_CTRL_TUNED_CLK) { host->tuning_done = true; return; } pr_warn("%s: HW tuning failed !\n", mmc_hostname(host->mmc)); break; } mdelay(1); } pr_info("%s: Tuning failed, falling back to fixed sampling clock\n", mmc_hostname(host->mmc)); sdhci_reset_tuning(host); } /* * This function is used to fix o2 dll shift issue. * It isn't necessary to detect card present before recovery. * Firstly, it is used by bht emmc card, which is embedded. * Second, before call recovery card present will be detected * outside of the execute tuning function. */ static int sdhci_o2_dll_recovery(struct sdhci_host *host) { int ret = 0; u8 scratch_8 = 0; u32 scratch_32 = 0; struct sdhci_pci_slot *slot = sdhci_priv(host); struct sdhci_pci_chip *chip = slot->chip; struct o2_host *o2_host = sdhci_pci_priv(slot); /* UnLock WP */ pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8); scratch_8 &= 0x7f; pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); while (o2_host->dll_adjust_count < DMDN_SZ && !ret) { /* Disable clock */ sdhci_writeb(host, 0, SDHCI_CLOCK_CONTROL); /* PLL software reset */ scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); scratch_32 |= O2_PLL_SOFT_RESET; sdhci_writel(host, scratch_32, O2_PLL_DLL_WDT_CONTROL1); pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG4, &scratch_32); /* Enable Base Clk setting change */ scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET; pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG4, scratch_32); o2_pci_set_baseclk(chip, dmdn_table[o2_host->dll_adjust_count]); /* Enable internal clock */ scratch_8 = SDHCI_CLOCK_INT_EN; sdhci_writeb(host, scratch_8, SDHCI_CLOCK_CONTROL); if (sdhci_o2_get_cd(host->mmc)) { /* * need wait at least 5ms for dll status stable, * after enable internal clock */ usleep_range(5000, 6000); if (sdhci_o2_wait_dll_detect_lock(host)) { scratch_8 |= SDHCI_CLOCK_CARD_EN; sdhci_writeb(host, scratch_8, SDHCI_CLOCK_CONTROL); ret = 1; } else { pr_warn("%s: DLL unlocked when dll_adjust_count is %d.\n", mmc_hostname(host->mmc), o2_host->dll_adjust_count); } } else { pr_err("%s: card present detect failed.\n", mmc_hostname(host->mmc)); break; } o2_host->dll_adjust_count++; } if (!ret && o2_host->dll_adjust_count == DMDN_SZ) pr_err("%s: DLL adjust over max times\n", mmc_hostname(host->mmc)); /* Lock WP */ pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8); scratch_8 |= 0x80; pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); return ret; } static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode) { struct sdhci_host *host = mmc_priv(mmc); struct sdhci_pci_slot *slot = sdhci_priv(host); struct sdhci_pci_chip *chip = slot->chip; int current_bus_width = 0; u32 scratch32 = 0; u16 scratch = 0; u8 scratch_8 = 0; u32 reg_val; /* * This handler implements the hardware tuning that is specific to * this controller. Fall back to the standard method for other TIMING. */ if ((host->timing != MMC_TIMING_MMC_HS200) && (host->timing != MMC_TIMING_UHS_SDR104) && (host->timing != MMC_TIMING_UHS_SDR50)) return sdhci_execute_tuning(mmc, opcode); if (WARN_ON(!mmc_op_tuning(opcode))) return -EINVAL; /* Force power mode enter L0 */ scratch = sdhci_readw(host, O2_SD_MISC_CTRL); scratch |= O2_SD_PWR_FORCE_L0; sdhci_writew(host, scratch, O2_SD_MISC_CTRL); /* Stop clk */ reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL); reg_val &= ~SDHCI_CLOCK_CARD_EN; sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL); if ((host->timing == MMC_TIMING_MMC_HS200) || (host->timing == MMC_TIMING_UHS_SDR104)) { /* UnLock WP */ pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8); scratch_8 &= 0x7f; pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); /* Set pcr 0x354[16] to choose dll clock, and set the default phase */ pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, ®_val); reg_val &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK); reg_val |= (O2_SD_SEL_DLL | O2_SD_FIX_PHASE); pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, reg_val); /* Lock WP */ pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8); scratch_8 |= 0x80; pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); } /* Start clk */ reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL); reg_val |= SDHCI_CLOCK_CARD_EN; sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL); /* wait DLL lock, timeout value 5ms */ if (readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host, scratch32, (scratch32 & O2_DLL_LOCK_STATUS), 1, 5000)) pr_warn("%s: DLL can't lock in 5ms after force L0 during tuning.\n", mmc_hostname(host->mmc)); /* * Judge the tuning reason, whether caused by dll shift * If cause by dll shift, should call sdhci_o2_dll_recovery */ if (!sdhci_o2_wait_dll_detect_lock(host)) if (!sdhci_o2_dll_recovery(host)) { pr_err("%s: o2 dll recovery failed\n", mmc_hostname(host->mmc)); return -EINVAL; } /* * o2 sdhci host didn't support 8bit emmc tuning */ if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) { current_bus_width = mmc->ios.bus_width; mmc->ios.bus_width = MMC_BUS_WIDTH_4; sdhci_set_bus_width(host, MMC_BUS_WIDTH_4); } sdhci_o2_set_tuning_mode(host); sdhci_start_tuning(host); __sdhci_o2_execute_tuning(host, opcode); sdhci_end_tuning(host); if (current_bus_width == MMC_BUS_WIDTH_8) { mmc->ios.bus_width = MMC_BUS_WIDTH_8; sdhci_set_bus_width(host, current_bus_width); } /* Cancel force power mode enter L0 */ scratch = sdhci_readw(host, O2_SD_MISC_CTRL); scratch &= ~(O2_SD_PWR_FORCE_L0); sdhci_writew(host, scratch, O2_SD_MISC_CTRL); sdhci_reset(host, SDHCI_RESET_CMD); sdhci_reset(host, SDHCI_RESET_DATA); host->flags &= ~SDHCI_HS400_TUNING; return 0; } static void o2_pci_led_enable(struct sdhci_pci_chip *chip) { int ret; u32 scratch_32; /* Set led of SD host function enable */ ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG0, &scratch_32); if (ret) return; scratch_32 &= ~O2_SD_FREG0_LEDOFF; pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG0, scratch_32); ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32); if (ret) return; scratch_32 |= O2_SD_LED_ENABLE; pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32); } static void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip) { u32 scratch_32; int ret; /* Improve write performance for SD3.0 */ ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32); if (ret) return; scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14)); pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32); /* Enable Link abnormal reset generating Reset */ ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32); if (ret) return; scratch_32 &= ~((1 << 19) | (1 << 11)); scratch_32 |= (1 << 10); pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32); /* set card power over current protection */ ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32); if (ret) return; scratch_32 |= (1 << 4); pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32); /* adjust the output delay for SD mode */ pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492); /* Set the output voltage setting of Aux 1.2v LDO */ ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32); if (ret) return; scratch_32 &= ~(3 << 12); pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32); /* Set Max power supply capability of SD host */ ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32); if (ret) return; scratch_32 &= ~(0x01FE); scratch_32 |= 0x00CC; pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32); /* Set DLL Tuning Window */ ret = pci_read_config_dword(chip->pdev, O2_SD_TUNING_CTRL, &scratch_32); if (ret) return; scratch_32 &= ~(0x000000FF); scratch_32 |= 0x00000066; pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32); /* Set UHS2 T_EIDLE */ ret = pci_read_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, &scratch_32); if (ret) return; scratch_32 &= ~(0x000000FC); scratch_32 |= 0x00000084; pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32); /* Set UHS2 Termination */ ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32); if (ret) return; scratch_32 &= ~((1 << 21) | (1 << 30)); pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32); /* Set L1 Entrance Timer */ ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32); if (ret) return; scratch_32 &= ~(0xf0000000); scratch_32 |= 0x30000000; pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32); ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_CTRL4, &scratch_32); if (ret) return; scratch_32 &= ~(0x000f0000); scratch_32 |= 0x00080000; pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32); } static void sdhci_pci_o2_enable_msi(struct sdhci_pci_chip *chip, struct sdhci_host *host) { int ret; ret = pci_find_capability(chip->pdev, PCI_CAP_ID_MSI); if (!ret) { pr_info("%s: unsupported MSI, use INTx irq\n", mmc_hostname(host->mmc)); return; } ret = pci_alloc_irq_vectors(chip->pdev, 1, 1, PCI_IRQ_MSI | PCI_IRQ_MSIX); if (ret < 0) { pr_err("%s: enable PCI MSI failed, err=%d\n", mmc_hostname(host->mmc), ret); return; } host->irq = pci_irq_vector(chip->pdev, 0); } static void sdhci_o2_enable_clk(struct sdhci_host *host, u16 clk) { /* Enable internal clock */ clk |= SDHCI_CLOCK_INT_EN; sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); sdhci_o2_enable_internal_clock(host); if (sdhci_o2_get_cd(host->mmc)) { clk |= SDHCI_CLOCK_CARD_EN; sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); } } static void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock) { u16 clk; u8 scratch; u32 scratch_32; struct sdhci_pci_slot *slot = sdhci_priv(host); struct sdhci_pci_chip *chip = slot->chip; host->mmc->actual_clock = 0; sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); if (clock == 0) return; /* UnLock WP */ pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); scratch &= 0x7f; pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); if ((host->timing == MMC_TIMING_UHS_SDR104) && (clock == 200000000)) { pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32); if ((scratch_32 & 0xFFFF0000) != 0x2c280000) o2_pci_set_baseclk(chip, 0x2c280000); } else { pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32); if ((scratch_32 & 0xFFFF0000) != 0x25100000) o2_pci_set_baseclk(chip, 0x25100000); } pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &scratch_32); scratch_32 &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK); pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, scratch_32); /* Lock WP */ pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); scratch |= 0x80; pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); sdhci_o2_enable_clk(host, clk); } static void sdhci_pci_o2_set_power(struct sdhci_host *host, unsigned char mode, unsigned short vdd) { struct sdhci_pci_chip *chip; struct sdhci_pci_slot *slot = sdhci_priv(host); chip = slot->chip; u8 scratch_8 = 0; u32 reg_val = 0; if(mode == MMC_POWER_OFF) { /* UnLock WP */ pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8); scratch_8 &= 0x7f; pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); /* Set pcr 0x354[16] to switch Clock Source back to OPE Clock */ pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, ®_val); reg_val &= ~(O2_SD_SEL_DLL); pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, reg_val); /* Lock WP */ pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8); scratch_8 |= 0x80; pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8); } sdhci_set_power(host, mode, vdd); } static int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot) { struct sdhci_pci_chip *chip; struct sdhci_host *host; struct o2_host *o2_host = sdhci_pci_priv(slot); u32 reg, caps; int ret; chip = slot->chip; host = slot->host; o2_host->dll_adjust_count = 0; caps = sdhci_readl(host, SDHCI_CAPABILITIES); /* * mmc_select_bus_width() will test the bus to determine the actual bus * width. */ if (caps & SDHCI_CAN_DO_8BIT) host->mmc->caps |= MMC_CAP_8_BIT_DATA; switch (chip->pdev->device) { case PCI_DEVICE_ID_O2_SDS0: case PCI_DEVICE_ID_O2_SEABIRD0: case PCI_DEVICE_ID_O2_SEABIRD1: case PCI_DEVICE_ID_O2_SDS1: case PCI_DEVICE_ID_O2_FUJIN2: reg = sdhci_readl(host, O2_SD_VENDOR_SETTING); if (reg & 0x1) host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12; host->quirks2 |= SDHCI_QUIRK2_BROKEN_DDR50; sdhci_pci_o2_enable_msi(chip, host); if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD0) { ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_SETTING, ®); if (ret) return -EIO; if (reg & (1 << 4)) { pr_info("%s: emmc 1.8v flag is set, force 1.8v signaling voltage\n", mmc_hostname(host->mmc)); host->flags &= ~SDHCI_SIGNALING_330; host->flags |= SDHCI_SIGNALING_180; host->mmc->caps2 |= MMC_CAP2_NO_SD; host->mmc->caps2 |= MMC_CAP2_NO_SDIO; pci_write_config_dword(chip->pdev, O2_SD_DETECT_SETTING, 3); } slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd; } if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD1) { slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd; host->mmc->caps2 |= MMC_CAP2_NO_SDIO; host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; } host->mmc_host_ops.execute_tuning = sdhci_o2_execute_tuning; if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2) break; /* set dll watch dog timer */ reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2); reg |= (1 << 12); sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2); break; default: break; } return 0; } static int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip) { int ret; u8 scratch; u32 scratch_32; switch (chip->pdev->device) { case PCI_DEVICE_ID_O2_8220: case PCI_DEVICE_ID_O2_8221: case PCI_DEVICE_ID_O2_8320: case PCI_DEVICE_ID_O2_8321: /* This extra setup is required due to broken ADMA. */ ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); if (ret) return ret; scratch &= 0x7f; pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); /* Set Multi 3 to VCC3V# */ pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08); /* Disable CLK_REQ# support after media DET */ ret = pci_read_config_byte(chip->pdev, O2_SD_CLKREQ, &scratch); if (ret) return ret; scratch |= 0x20; pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch); /* Choose capabilities, enable SDMA. We have to write 0x01 * to the capabilities register first to unlock it. */ ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch); if (ret) return ret; scratch |= 0x01; pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch); pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73); /* Disable ADMA1/2 */ pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39); pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08); /* Disable the infinite transfer mode */ ret = pci_read_config_byte(chip->pdev, O2_SD_INF_MOD, &scratch); if (ret) return ret; scratch |= 0x08; pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch); /* Lock WP */ ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); if (ret) return ret; scratch |= 0x80; pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); break; case PCI_DEVICE_ID_O2_SDS0: case PCI_DEVICE_ID_O2_SDS1: case PCI_DEVICE_ID_O2_FUJIN2: /* UnLock WP */ ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); if (ret) return ret; scratch &= 0x7f; pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); /* DevId=8520 subId= 0x11 or 0x12 Type Chip support */ if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) { ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG0, &scratch_32); if (ret) return ret; scratch_32 = ((scratch_32 & 0xFF000000) >> 24); /* Check Whether subId is 0x11 or 0x12 */ if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) { scratch_32 = 0x25100000; o2_pci_set_baseclk(chip, scratch_32); ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG4, &scratch_32); if (ret) return ret; /* Enable Base Clk setting change */ scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET; pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG4, scratch_32); /* Set Tuning Window to 4 */ pci_write_config_byte(chip->pdev, O2_SD_TUNING_CTRL, 0x44); break; } } /* Enable 8520 led function */ o2_pci_led_enable(chip); /* Set timeout CLK */ ret = pci_read_config_dword(chip->pdev, O2_SD_CLK_SETTING, &scratch_32); if (ret) return ret; scratch_32 &= ~(0xFF00); scratch_32 |= 0x07E0C800; pci_write_config_dword(chip->pdev, O2_SD_CLK_SETTING, scratch_32); ret = pci_read_config_dword(chip->pdev, O2_SD_CLKREQ, &scratch_32); if (ret) return ret; scratch_32 |= 0x3; pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32); ret = pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32); if (ret) return ret; scratch_32 &= ~(0x1F3F070E); scratch_32 |= 0x18270106; pci_write_config_dword(chip->pdev, O2_SD_PLL_SETTING, scratch_32); /* Disable UHS1 funciton */ ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG2, &scratch_32); if (ret) return ret; scratch_32 &= ~(0xE0); pci_write_config_dword(chip->pdev, O2_SD_CAP_REG2, scratch_32); if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) sdhci_pci_o2_fujin2_pci_init(chip); /* Lock WP */ ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); if (ret) return ret; scratch |= 0x80; pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); break; case PCI_DEVICE_ID_O2_SEABIRD0: case PCI_DEVICE_ID_O2_SEABIRD1: /* UnLock WP */ ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); if (ret) return ret; scratch &= 0x7f; pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); ret = pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32); if (ret) return ret; if ((scratch_32 & 0xff000000) == 0x01000000) { scratch_32 &= 0x0000FFFF; scratch_32 |= 0x1F340000; pci_write_config_dword(chip->pdev, O2_SD_PLL_SETTING, scratch_32); } else { scratch_32 &= 0x0000FFFF; scratch_32 |= 0x25100000; pci_write_config_dword(chip->pdev, O2_SD_PLL_SETTING, scratch_32); ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG4, &scratch_32); if (ret) return ret; scratch_32 |= (1 << 22); pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG4, scratch_32); } /* Set Tuning Windows to 5 */ pci_write_config_byte(chip->pdev, O2_SD_TUNING_CTRL, 0x55); //Adjust 1st and 2nd CD debounce time pci_read_config_dword(chip->pdev, O2_SD_MISC_CTRL2, &scratch_32); scratch_32 &= 0xFFE7FFFF; scratch_32 |= 0x00180000; pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL2, scratch_32); pci_write_config_dword(chip->pdev, O2_SD_DETECT_SETTING, 1); /* Lock WP */ ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); if (ret) return ret; scratch |= 0x80; pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); break; } return 0; } #ifdef CONFIG_PM_SLEEP static int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip) { sdhci_pci_o2_probe(chip); return sdhci_pci_resume_host(chip); } #endif static const struct sdhci_ops sdhci_pci_o2_ops = { .set_clock = sdhci_pci_o2_set_clock, .enable_dma = sdhci_pci_enable_dma, .set_bus_width = sdhci_set_bus_width, .reset = sdhci_reset, .set_uhs_signaling = sdhci_set_uhs_signaling, .set_power = sdhci_pci_o2_set_power, }; const struct sdhci_pci_fixes sdhci_o2 = { .probe = sdhci_pci_o2_probe, .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD, .probe_slot = sdhci_pci_o2_probe_slot, #ifdef CONFIG_PM_SLEEP .resume = sdhci_pci_o2_resume, #endif .ops = &sdhci_pci_o2_ops, .priv_size = sizeof(struct o2_host), }; ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: Bug: After a 'warm' reboot the disk is missing (not detected by the bios) on a HP t640 2024-01-19 8:40 ` 回复: " Fred Ai(WH) @ 2024-01-22 15:52 ` Ben Mesman | Spark Narrowcasting 0 siblings, 0 replies; 9+ messages in thread From: Ben Mesman | Spark Narrowcasting @ 2024-01-22 15:52 UTC (permalink / raw) To: Fred Ai(WH), Sean Christopherson Cc: Thomas Gleixner, Ingo Molnar, Borislav Petkov, Dave Hansen, x86@kernel.org, linux-kernel@vger.kernel.org, Ulf Hansson, Adrian Hunter, Chevron Li (WH), Shaper Liu (WH) Helllo Fred Ai, > Hi Ben Mesman, > I changed the code by using "set_power" to recover clock source when power off card and provide the attachment code try to fix this issue, but I didn't test this path code. You can test attachment patch code > and give the feedback to me. I tested the attachment and this patch solves my issue, the HP t640 will now succesfully do a warm reboot. Thank you for your patience and amazing work. Looking forward to sseing this patch in the mailline kernels :-) Kind regards, Ben Mesman. ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2024-01-22 15:52 UTC | newest]
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2023-12-20 16:47 ` Bug: After a 'warm' reboot the disk is missing (not detected by the bios) on a HP t640 Sean Christopherson
2023-12-28 12:39 ` Ben Mesman | Spark Narrowcasting
2024-01-02 17:58 ` Sean Christopherson
2024-01-03 12:23 ` 回复: " Fred Ai(WH)
2024-01-04 10:31 ` Ben Mesman | Spark Narrowcasting
2024-01-08 2:02 ` 回复: " Fred Ai(WH)
2024-01-09 12:25 ` Ben Mesman | Spark Narrowcasting
2024-01-19 8:40 ` 回复: " Fred Ai(WH)
2024-01-22 15:52 ` Ben Mesman | Spark Narrowcasting
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