Re: [External] Re: [PATCH] serial: 8250: fix panic due to PSLVERR

[Andy Shevchenko <andriy.shevchenko@linux.intel.com>]

On Mon, Apr 07, 2025 at 09:22:08PM +0800, yunhui cui wrote:
> On Fri, Apr 4, 2025 at 6:58 PM Andy Shevchenko
> <andriy.shevchenko@linux.intel.com> wrote:
> > On Fri, Apr 04, 2025 at 10:44:09AM +0800, yunhui cui wrote:
> > > On Thu, Apr 3, 2025 at 7:36 PM Andy Shevchenko
> > > <andriy.shevchenko@linux.intel.com> wrote:
> > > > On Thu, Apr 03, 2025 at 05:03:36PM +0800, Yunhui Cui wrote:

...

> > > > > To resolve this issue, relevant serial_port_out operations should be
> > > >
> > > > serial_port_out()
> > >
> > > Okay.
> > >
> > > > > placed in a critical section, and UART_RX data should only be read
> > > > > when the UART_LSR DR bit is set.
> > > >
> > > > The last one is made in the common code, are you sure that all supported UARTs
> > > > will be okay with such a change?
> > >
> > > This change enhances code robustness without being intrusive.
> >
> > It is intrusive as it touches the core part affecting basically
> > _all_ of the 8250-based drivers.
> >
> > Yes, it's small, but still it needs to be done carefully with commit message
> > pointing out to the other 8250 datasheets to show that this is _not_ DW
> > specific change.
> 
> serial8250_clear_fifos is already part of the serial8250_do_startup
> process. The purpose of adding it to the critical section is to
> prevent the FIFO from being cleared while the UART is in use.
> 
> Similarly, serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
> 
> It is a correct logic to check if the data is ready before reading,
> which prevents the FIFO from being enabled by other CPUs before
> executing serial_port_in(port, UART_RX).

Yes, I understand what you are doing there, my question is about possible
side-effects on non-DW (non-Synopsys) IPs.

-- 
With Best Regards,
Andy Shevchenko