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[34.87.152.188]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-739d97ee90asm9907314b3a.57.2025.04.07.22.30.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Apr 2025 22:30:49 -0700 (PDT) Date: Tue, 8 Apr 2025 05:30:41 +0000 From: Pranjal Shrivastava To: "Aneesh Kumar K.V (Arm)" Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, will@kernel.org, robin.murphy@arm.com, jgg@ziepe.ca, nicolinc@nvidia.com, jsnitsel@redhat.com, kevin.tian@intel.com, ddutile@redhat.com Subject: Re: [PATCH] iommu/arm-smmu-v3: Add missing S2FWB feature detection Message-ID: References: <20250408033351.1012411-1-aneesh.kumar@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250408033351.1012411-1-aneesh.kumar@kernel.org> On Tue, Apr 08, 2025 at 09:03:51AM +0530, Aneesh Kumar K.V (Arm) wrote: > Commit 67e4fe398513 ("iommu/arm-smmu-v3: Use S2FWB for NESTED domains") > introduced S2FWB usage but omitted the corresponding feature detection. > As a result, vIOMMU allocation fails on FVP in arm_vsmmu_alloc(), due to > the following check: > > if (!arm_smmu_master_canwbs(master) && > !(smmu->features & ARM_SMMU_FEAT_S2FWB)) > return ERR_PTR(-EOPNOTSUPP); > > This patch adds the missing detection logic to prevent allocation > failure when S2FWB is supported. > > Fixes: 67e4fe398513 ("iommu/arm-smmu-v3: Use S2FWB for NESTED domains") > Signed-off-by: Aneesh Kumar K.V (Arm) > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > index 358072b4e293..c7d297ceabdb 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -4405,6 +4405,8 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) > reg = readl_relaxed(smmu->base + ARM_SMMU_IDR3); > if (FIELD_GET(IDR3_RIL, reg)) > smmu->features |= ARM_SMMU_FEAT_RANGE_INV; > + if (FIELD_GET(IDR3_FWB, reg)) > + smmu->features |= ARM_SMMU_FEAT_S2FWB; > > /* IDR5 */ > reg = readl_relaxed(smmu->base + ARM_SMMU_IDR5); Indeed. Looks like setting the feature flag was missed previously. Reviewed-by: Pranjal Shrivastava Thanks, Praan