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From: Ingo Molnar <mingo@kernel.org>
To: Mario Limonciello <superm1@kernel.org>
Cc: "Borislav Petkov" <bp@alien8.de>,
	"Jean Delvare" <jdelvare@suse.com>,
	"Andi Shyti" <andi.shyti@kernel.org>,
	"Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>,
	"Jonathan Corbet" <corbet@lwn.net>,
	"Mario Limonciello" <mario.limonciello@amd.com>,
	"Yazen Ghannam" <yazen.ghannam@amd.com>,
	"Thomas Gleixner" <tglx@linutronix.de>,
	"Ingo Molnar" <mingo@redhat.com>,
	"Dave Hansen" <dave.hansen@linux.intel.com>,
	"maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)"
	<x86@kernel.org>, "H . Peter Anvin" <hpa@zytor.com>,
	"Shyam Sundar S K" <Shyam-sundar.S-k@amd.com>,
	"Hans de Goede" <hdegoede@redhat.com>,
	"open list:DOCUMENTATION" <linux-doc@vger.kernel.org>,
	"open list" <linux-kernel@vger.kernel.org>,
	"open list:I2C/SMBUS CONTROLLER DRIVERS FOR PC"
	<linux-i2c@vger.kernel.org>,
	"open list:AMD PMC DRIVER" <platform-driver-x86@vger.kernel.org>
Subject: Re: [PATCH v3 4/4] x86/CPU/AMD: Print the reason for the last reset
Date: Sat, 12 Apr 2025 21:37:56 +0200	[thread overview]
Message-ID: <Z_rBFMp34zIYkRwh@gmail.com> (raw)
In-Reply-To: <42b7547d-c1f7-4509-a381-7bf0a485a5f5@kernel.org>


* Mario Limonciello <superm1@kernel.org> wrote:

> 
> 
> On 4/11/25 07:06, Borislav Petkov wrote:
> > On Thu, Apr 10, 2025 at 03:02:02PM -0500, Mario Limonciello wrote:
> > > +static __init int print_s5_reset_status_mmio(void)
> > > +{
> > > +	void __iomem *addr;
> > > +	unsigned long value;
> > > +	int bit = -1;
> > > +
> > > +	if (!cpu_feature_enabled(X86_FEATURE_ZEN))
> > > +		return 0;
> > > +
> > > +	addr = ioremap(FCH_PM_BASE + FCH_PM_S5_RESET_STATUS, sizeof(value));
> > > +	if (!addr)
> > > +		return 0;
> > 
> > newline.
> > 
> > > +	value = ioread32(addr);
> > > +	iounmap(addr);
> > > +
> > > +	do {
> > > +		bit = find_next_bit(&value, BITS_PER_LONG, bit + 1);
> > > +	} while (!s5_reset_reason_txt[bit]);
> > 
> > What's the idea here? The highest bit is the most fitting one?
> > 
> > So why don't you do fls() or so?
> 
> The idea was to walk all the bits and pick the first one that has a string
> associated with it.  I was finding that sometimes the reserved bits are set
> which would get you a NULL pointer deref.

Would it be possible for firmware to set multiple bits with a text 
behind it?

BTW:

+       [32] = "unknown",

but BITS_PER_LONG is 64 on x86-64, not 32. How is that supposed to 
work?

Anyway, in terms of robustness, it would be best to assume nothing 
about the structure of the bitmask, and do something straightforward 
like this:

	unsigned long value;
	int nr_reasons = 0;
	int bit = -1;

	...

	/* Iterate on each bit in the 'value' mask: */

	for (;;) {
		bit = find_next_bit(&value, BITS_PER_LONG, bit + 1);

		/* Reached the end of the word, no more bits: */
		if (bit >= BITS_PER_LONG) {
			if (!nr_reasons)
				pr_info("x86/amd: Previous system reset reason [0x%08lx]: Unknown\n", value);
			break;
		}

		nr_reasons++;
		pr_info("x86/amd: Previous system reset reason [0x%08lx]: %s\n",
			value, s5_reset_reason_txt[bit]);
	}

which prints out multiple bits as well, and does the right thing if no 
bit is found, without having to encode BITS_PER_LONG in the 
s5_reset_reason_txt[] array.

And BTW: thanks for implementing this. :-)

Thanks,

	Ingo

      parent reply	other threads:[~2025-04-12 19:38 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-10 20:01 [PATCH v3 0/4] AMD Zen debugging documentation Mario Limonciello
2025-04-10 20:01 ` [PATCH v3 1/4] Documentation: Add AMD Zen debugging document Mario Limonciello
2025-04-12  2:12   ` Bagas Sanjaya
2025-04-12  2:19     ` Mario Limonciello
2025-04-12  2:28       ` Bagas Sanjaya
2025-04-10 20:02 ` [PATCH v3 2/4] i2c: piix4: Move SB800_PIIX4_FCH_PM_ADDR definition to amd_node.h Mario Limonciello
2025-04-11 11:49   ` Borislav Petkov
2025-04-11 12:09     ` Mario Limonciello
2025-04-11 12:41       ` Borislav Petkov
2025-04-12 19:44         ` Ingo Molnar
2025-04-12 19:51           ` Mario Limonciello
2025-04-12 20:15             ` Ingo Molnar
2025-04-12 20:23               ` Mario Limonciello
2025-04-12 20:47                 ` Ingo Molnar
2025-04-12 22:29               ` Borislav Petkov
2025-04-13  7:54                 ` Ingo Molnar
2025-04-13  8:44                   ` Ingo Molnar
2025-04-13 19:27                     ` Mario Limonciello
2025-04-13 19:32                       ` Ingo Molnar
2025-04-11 21:15   ` kernel test robot
2025-04-11 21:56   ` kernel test robot
2025-04-10 20:02 ` [PATCH v3 3/4] platform/x86/amd: pmc: use FCH_PM_BASE definition Mario Limonciello
2025-04-10 20:02 ` [PATCH v3 4/4] x86/CPU/AMD: Print the reason for the last reset Mario Limonciello
2025-04-11 12:06   ` Borislav Petkov
2025-04-11 12:12     ` Mario Limonciello
2025-04-11 12:50       ` Borislav Petkov
2025-04-11 13:25         ` Mario Limonciello
2025-04-12 19:37       ` Ingo Molnar [this message]

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