Re: [PATCH v3 4/4] arm64: dts: rockchip: Add devicetree for Pine64 PineTab2

Ondřej Jirman
2024-01-02T21:18:52Z

On Tue, Jan 02, 2024 at 09:56:20PM +0100, Jonas Karlman wrote:
> Hi Manuel and Ondřej,
>
> On 2024-01-02 19:07, Ondřej Jirman wrote:
> > Hello Manuel,
>
> [...]
>
> >> +
> >> +&sfc {
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&fspi_dual_io_pins>;
> >> + status = "okay";
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + flash@0 {
> >> + compatible = "jedec,spi-nor";
> >> + reg = <0>;
> >> + spi-max-frequency = <24000000>;
> >
> > That's a bit on the low side. The flash chip should work for all commands up to
> > 80MHz https://megous.com/dl/tmp/b428ad9b85ac4633.png and SGM3157YC6 switch
> > for the FSPI-CLK should have high enough bandwidth, too.
>
> I agree that this is a little bit on the low side, it was a safe rate
> that I used for U-Boot. U-Boot required an exact rate of the supported
> sfc clk rates: 24, 50, 75, 100, 125 or 150 MHz.
>
> Please also note that the SPI NOR flash chip used in PineTab2 is not a
> GigaDevice GD25LQ128E, it should be a SiliconKaiser SK25LP128, same as
> found in the Pine64 PinePhone Pro.

According to this http://en.siliconkaiser.com/pro/ it should maybe go up to
133MHz. No idea what's the difference between LP vs LE variant. So it may work
with 100 MHz.

On Pinephone Pro variants with nerfed SPI CLK signal integrity (any variant with
RE instead of a RESET button - so all production batches), anything above 10 MHz
has real trouble working. But this should not be the case here with PT2, looking
at the schematic...

Anyway, it's a nice to have.

> >
> >> + spi-rx-bus-width = <2>;
> >
> > GD25LQ128E supports quad I/O. Maybe try 4 if it will work.
>
> The schematic only shows fspi D0 and D1 connected, and use the D2 line
> for eMMC_RSTn, so spi-rx-bus-width = <2> should be correct.

Ah, I see.

regards,
o.

> >
> >> + spi-tx-bus-width = <1>;
> >> + };
> >> +};
> >> +
>
> Regards,
> Jonas