From: Mark Rutland <mark.rutland@arm.com>
To: Easwar Hariharan <eahariha@linux.microsoft.com>
Cc: Oliver Upton <oliver.upton@linux.dev>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Jonathan Corbet <corbet@lwn.net>,
Marc Zyngier <maz@kernel.org>,
Andre Przywara <andre.przywara@arm.com>,
Rob Herring <robh@kernel.org>, Zenghui Yu <yuzenghui@huawei.com>,
"moderated list:ARM64 PORT (AARCH64 ARCHITECTURE)"
<linux-arm-kernel@lists.infradead.org>,
"open list:DOCUMENTATION" <linux-doc@vger.kernel.org>,
open list <linux-kernel@vger.kernel.org>,
Anshuman Khandual <anshuman.khandual@arm.com>,
stable@vger.kernel.org
Subject: Re: [PATCH] arm64: Subscribe Microsoft Azure Cobalt 100 to ARM Neoverse N2 errata
Date: Wed, 14 Feb 2024 11:11:14 +0000 [thread overview]
Message-ID: <Zcyf0oIJe7ukH0si@FVFF77S0Q05N> (raw)
In-Reply-To: <18b3ac3e-2bfc-4fce-9be4-3e75e487f9fc@linux.microsoft.com>
On Tue, Feb 13, 2024 at 04:19:08PM -0800, Easwar Hariharan wrote:
> >> diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
> >> index 7c7493cb571f..a632a7514e55 100644
> >> --- a/arch/arm64/include/asm/cputype.h
> >> +++ b/arch/arm64/include/asm/cputype.h
> >> @@ -61,6 +61,7 @@
> >> #define ARM_CPU_IMP_HISI 0x48
> >> #define ARM_CPU_IMP_APPLE 0x61
> >> #define ARM_CPU_IMP_AMPERE 0xC0
> >> +#define ARM_CPU_IMP_MICROSOFT 0x6D
> >>
> >> #define ARM_CPU_PART_AEM_V8 0xD0F
> >> #define ARM_CPU_PART_FOUNDATION 0xD00
> >> @@ -135,6 +136,8 @@
> >>
> >> #define AMPERE_CPU_PART_AMPERE1 0xAC3
> >>
> >> +#define MSFT_CPU_PART_AZURE_COBALT_100 0xD49 /* Based on r0p0 of ARM Neoverse N2 */
> >> +
> >> #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
> >> #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
> >> #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
> >> @@ -193,6 +196,7 @@
> >> #define MIDR_APPLE_M2_BLIZZARD_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_MAX)
> >> #define MIDR_APPLE_M2_AVALANCHE_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX)
> >> #define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)
> >> +#define MIDR_MICROSOFT_AZURE_COBALT_100 MIDR_CPU_MODEL(ARM_CPU_IMP_MICROSOFT, MSFT_CPU_PART_AZURE_COBALT_100)
> >
> > nitpick: consistently use the abbreviated 'MSFT' for all the definitions
> > you're adding.
>
> I was rather hoping to use Microsoft throughout, but I chose MSFT for the CPU_PART* to align columns
> with the other defines. :) If consistency is of a higher priority than column alignment, I can change it
> to MICROSOFT rather than MSFT throughout.
Consistency across the definitions is more important than alignmen; please
choose either "MSFT" or "MICROSOFT" and use that consistently.
Mark.
next prev parent reply other threads:[~2024-02-14 11:11 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-12 23:29 [PATCH] arm64: Subscribe Microsoft Azure Cobalt 100 to ARM Neoverse N2 errata Easwar Hariharan
2024-02-12 23:44 ` Oliver Upton
2024-02-14 0:19 ` Easwar Hariharan
2024-02-14 11:11 ` Mark Rutland [this message]
2024-02-15 22:53 ` Easwar Hariharan
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