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[84.236.113.97]) by smtp.gmail.com with ESMTPSA id f8-20020a056402150800b0056e0988bccesm329848edw.31.2024.04.03.01.06.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:06:13 -0700 (PDT) Sender: Ingo Molnar Date: Wed, 3 Apr 2024 10:06:11 +0200 From: Ingo Molnar To: Andrii Nakryiko Cc: Andrii Nakryiko , x86@kernel.org, peterz@infradead.org, mingo@redhat.com, tglx@linutronix.de, bpf@vger.kernel.org, linux-kernel@vger.kernel.org, jolsa@kernel.org, song@kernel.org, kernel-team@meta.com Subject: Re: [PATCH v4 0/4] perf/x86/amd: add LBR capture support outside of hardware events Message-ID: References: <20240331041830.2806741-1-andrii@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: * Andrii Nakryiko wrote: > On Mon, Apr 1, 2024 at 2:30 AM Ingo Molnar wrote: > > > > > > * Andrii Nakryiko wrote: > > > > > Add AMD-specific implementation of perf_snapshot_branch_stack static call that > > > allows LBR capture from arbitrary points in the kernel. This is utilized by > > > BPF programs. See patch #3 for all the details. > > > > > > Patches #1 and #2 are preparatory steps to ensure LBR freezing is completely > > > inlined and have no branches, to minimize LBR snapshot contamination. > > > > > > Patch #4 removes an artificial restriction on perf events with LBR enabled. > > > > > > Andrii Nakryiko (4): > > > perf/x86/amd: ensure amd_pmu_core_disable_all() is always inlined > > > perf/x86/amd: avoid taking branches before disabling LBR > > > perf/x86/amd: support capturing LBR from software events > > > perf/x86/amd: don't reject non-sampling events with configured LBR > > > > > > arch/x86/events/amd/core.c | 37 +++++++++++++++++++++++++++++++++++- > > > arch/x86/events/amd/lbr.c | 11 +---------- > > > arch/x86/events/perf_event.h | 11 +++++++++++ > > > 3 files changed, 48 insertions(+), 11 deletions(-) > > > > So there's a new conflict with patch #2, probably due to interaction > > with this recent fix that is now upstream: > > > > 598c2fafc06f ("perf/x86/amd/lbr: Use freeze based on availability") > > > > I don't think it should change the logic of the snapshot feature > > materially, X86_FEATURE_AMD_LBR_PMC_FREEZE should be orthogonal to it, > > as the LBR snapshot isn't taken from a PMI. > > > > Yep, seems like there was a parallel change to related code in > perf/urgent branch. And yes, you are right that it's orthogonal and > doesn't regress anything as far as branching and whatnot (just > retested everything on real hardware). So I've rebased my patches on > top of perf/urgent, will send v5 momentarily. Thank you - it's now all in tip:perf/core and lined up for v6.10. > Sorry for an extra round on this. Not your doing really - just crossing patches. Thanks, Ingo