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AJvYcCU/4dZ0E/U0TuwTJWUnVQsXcPYu4DRBznS27RpZQrIYEc+Dp2wTni57Y/2t0LBB8sGIqDDcmXeZVYjoA8R/PSAOx+0bZauk5tfN9y++ X-Gm-Message-State: AOJu0YxT4IHkES09cWfnx+DCxPm/Aj7oMIyViYwoUaowI+/s7Zf2LOe1 Xn5DxilndC7NJ/MM1Qpa8gQxTzidliqqEr1VEZGvVbuZqnlneLUzvGRpeDhQkMiIssGxbfs2YTL M X-Google-Smtp-Source: AGHT+IEfI6/ElqbxX011QI3EBz6Tqo72909UkKh+kFTHngulAL02ypmJA9aR2eFcAe+MhiuYzBH3uw== X-Received: by 2002:a17:906:2654:b0:a4d:d356:fd69 with SMTP id i20-20020a170906265400b00a4dd356fd69mr219001ejc.12.1711658346886; Thu, 28 Mar 2024 13:39:06 -0700 (PDT) Received: from linaro.org ([79.114.172.194]) by smtp.gmail.com with ESMTPSA id mf9-20020a170906cb8900b00a46faaf7427sm1133467ejb.121.2024.03.28.13.39.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Mar 2024 13:39:06 -0700 (PDT) Date: Thu, 28 Mar 2024 22:39:04 +0200 From: Abel Vesa To: Kuogee Hsieh Cc: dri-devel@lists.freedesktop.org, robdclark@gmail.com, sean@poorly.run, swboyd@chromium.org, dianders@chromium.org, vkoul@kernel.org, daniel@ffwll.ch, airlied@gmail.com, agross@kernel.org, dmitry.baryshkov@linaro.org, andersson@kernel.org, quic_abhinavk@quicinc.com, quic_jesszhan@quicinc.com, quic_sbillaka@quicinc.com, marijn.suijten@somainline.org, freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v1] drm/msm/dp: assign correct DP controller ID to interface table Message-ID: References: <1711656246-3483-1-git-send-email-quic_khsieh@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1711656246-3483-1-git-send-email-quic_khsieh@quicinc.com> On 24-03-28 13:04:05, Kuogee Hsieh wrote: > At current x1e80100 interface table, interface #3 is wrongly > connected to DP controller #0 and interface #4 wrongly connected > to DP controller #2. Fix this problem by connect Interface #3 to > DP controller #0 and interface #4 connect to DP controller #1. > Also add interface #6, #7 and #8 connections to DP controller to > complete x1e80100 interface table. > > Signed-off-by: Kuogee Hsieh > --- Nitpick: Probably mention the x1e80100 in the subject line somehow. Reviewed-by: Abel Vesa > .../drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 34 ++++++++++++++++++++-- > 1 file changed, 31 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h > index 9a9f709..a3e60ac 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h > @@ -324,6 +324,7 @@ static const struct dpu_wb_cfg x1e80100_wb[] = { > }, > }; > > +/* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */ > static const struct dpu_intf_cfg x1e80100_intf[] = { > { > .name = "intf_0", .id = INTF_0, > @@ -358,8 +359,8 @@ static const struct dpu_intf_cfg x1e80100_intf[] = { > .name = "intf_3", .id = INTF_3, > .base = 0x37000, .len = 0x280, > .features = INTF_SC7280_MASK, > - .type = INTF_DP, > - .controller_id = MSM_DP_CONTROLLER_1, > + .type = INTF_NONE, > + .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ > .prog_fetch_lines_worst_case = 24, > .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), > .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), > @@ -368,7 +369,7 @@ static const struct dpu_intf_cfg x1e80100_intf[] = { > .base = 0x38000, .len = 0x280, > .features = INTF_SC7280_MASK, > .type = INTF_DP, > - .controller_id = MSM_DP_CONTROLLER_2, > + .controller_id = MSM_DP_CONTROLLER_1, > .prog_fetch_lines_worst_case = 24, > .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20), > .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21), > @@ -381,6 +382,33 @@ static const struct dpu_intf_cfg x1e80100_intf[] = { > .prog_fetch_lines_worst_case = 24, > .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22), > .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23), > + }, { > + .name = "intf_6", .id = INTF_6, > + .base = 0x3A000, .len = 0x280, > + .features = INTF_SC7280_MASK, > + .type = INTF_DP, > + .controller_id = MSM_DP_CONTROLLER_2, > + .prog_fetch_lines_worst_case = 24, > + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17), > + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16), > + }, { > + .name = "intf_7", .id = INTF_7, > + .base = 0x3b000, .len = 0x280, > + .features = INTF_SC7280_MASK, > + .type = INTF_NONE, > + .controller_id = MSM_DP_CONTROLLER_2, /* pair with intf_6 for DP MST */ > + .prog_fetch_lines_worst_case = 24, > + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18), > + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 19), > + }, { > + .name = "intf_8", .id = INTF_8, > + .base = 0x3c000, .len = 0x280, > + .features = INTF_SC7280_MASK, > + .type = INTF_NONE, > + .controller_id = MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */ > + .prog_fetch_lines_worst_case = 24, > + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), > + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), > }, > }; > > -- > 2.7.4 >