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[31.46.241.165]) by smtp.gmail.com with ESMTPSA id q18-20020aa7d452000000b0056e247de8e3sm6418852edr.1.2024.04.10.05.58.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Apr 2024 05:58:02 -0700 (PDT) Sender: Ingo Molnar Date: Wed, 10 Apr 2024 14:58:00 +0200 From: Ingo Molnar To: Ard Biesheuvel Cc: linux-kernel@vger.kernel.org, x86@kernel.org, Ard Biesheuvel , Conrad Grobler , Kevin Loughlin Subject: Re: [PATCH] x86/boot/64: Clear CR4.PGE to disable global 1:1 mappings Message-ID: References: <20240410102520.348017-2-ardb+git@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240410102520.348017-2-ardb+git@google.com> * Ard Biesheuvel wrote: > From: Ard Biesheuvel > > The early 64-bit boot code must be entered with a 1:1 mapping of the > bootable image, but it cannot operate without a 1:1 mapping of all the > assets in memory that it accesses, and therefore, it creates such > mappings for all known assets upfront, and additional ones on demand > when a page fault happens on a memory address. > > These mappings are created with the global bit G set, as the flags used > to create page table descriptors are based on __PAGE_KERNEL_LARGE_EXEC > defined by the core kernel, even though the context where these mappings > are used is very different. > > This means that the TLB maintenance carried out by the decompressor is > not sufficient if it is entered with CR4.PGE enabled, which has been > observed to happen with the stage0 bootloader of project Oak. While this > is a dubious practice if no global mappings are being used to begin > with, the decompressor is clearly at fault here for creating global > mappings and not performing the appropriate TLB maintenance. > > Since commit > > f97b67a773cd84b ("x86/decompressor: Only call the trampoline when changing paging levels") > > CR4 is no longer modified by the decompressor if no change in the number > of paging levels is needed. Before that, CR4 would always be set to a > known value with PGE cleared. So if we do this for robustness & historical pre-f97b67a773cd84b quirk-reliance's sake, I'd prefer if we loaded a known CR4 value again, instead of just turning off the PGE bit. It's probably also a tiny bit faster, as no CR4 read has to be performed. Thanks, Ingo