[RFC PATCH 12/12] riscv: enable kernel shadow stack and landing pad enforcement

Deepak Gupta
2024-04-09T06:12:22Z

This patch enables kernel shadow stack and landing pad enforcement by
invoking a SBI call. As of now it just issues a SBI_EXT_BASE and a hacked
up opensbi implementation sets the LPE/SSE bits in menvcfg

Eventually, we should have fwft [1] interface using which kernel should be
able to set this enforcement properly

[1] - https://lists.riscv.org/g/tech-prs/message/833

Signed-off-by: Deepak Gupta <debug@rivosinc.com>
---
arch/riscv/kernel/head.S | 14 ++++++++++++++
1 file changed, 14 insertions(+)

diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index bc248c137c90..1e5bc7b2ee75 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -164,6 +164,13 @@ secondary_start_sbi:
call relocate_enable_mmu
#endif
call .Lsetup_trap_vector
+ /*
+ * Temp hack to get menvcfg.SSE=1 and menvcfg.LPE=1 by invoking
+ * SBI_EXT_BASE
+ */
+ li a6, 0
+ li a7, 0x10
+ ecall
scs_load_current t0
lui t2, 0x1
tail smp_callin
@@ -313,6 +320,13 @@ SYM_CODE_START(_start_kernel)
la tp, init_task
la sp, init_thread_union + THREAD_SIZE
addi sp, sp, -PT_SIZE_ON_STACK
+ /*
+ * Temp hack to get menvcfg.SSE=1 and menvcfg.LPE=1 by invoking
+ * SBI_EXT_BASE
+ */
+ li a6, 0
+ li a7, 0x10
+ ecall
scs_load_current t0

#ifdef CONFIG_KASAN
--
2.43.2