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AJvYcCWu1XMNUcZctAJWZZ5j33cZKbeufBBRrmJi5N6eH2GdOqu80CDLHwN9o6JRi7c7V7QWzq7rqA8eulWpg3O3vGKwfzJK3+gic2srA6Z3 X-Gm-Message-State: AOJu0Yx/bIKiooSJneCu+Lfaw1nO6Bg2xiQB9DNRNw7Y6JIDibcaUE8s gYxl5pJK3e8ScdW01Ao9SHMqQHp77cJaKXJJoAbYgaye15eqvrUG1twDTwRoTAmWu8YBHBgCM3Y JGQ== X-Google-Smtp-Source: AGHT+IH5Jbyvd3OHt3LMjFeRYVLdua5jhWirNWwQZU+zhsPQlAr4tntyRhPDF3UtZtz+lXOjBlBpJeVMz/c= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a05:6902:100a:b0:dd9:2782:d1c6 with SMTP id w10-20020a056902100a00b00dd92782d1c6mr263457ybt.1.1714605330246; Wed, 01 May 2024 16:15:30 -0700 (PDT) Date: Wed, 1 May 2024 16:15:28 -0700 In-Reply-To: <20240219074733.122080-25-weijiang.yang@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240219074733.122080-1-weijiang.yang@intel.com> <20240219074733.122080-25-weijiang.yang@intel.com> Message-ID: Subject: Re: [PATCH v10 24/27] KVM: x86: Enable CET virtualization for VMX and advertise to userspace From: Sean Christopherson To: Yang Weijiang Cc: pbonzini@redhat.com, dave.hansen@intel.com, x86@kernel.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, peterz@infradead.org, chao.gao@intel.com, rick.p.edgecombe@intel.com, mlevitsk@redhat.com, john.allen@amd.com Content-Type: text/plain; charset="us-ascii" On Sun, Feb 18, 2024, Yang Weijiang wrote: > @@ -696,6 +697,20 @@ void kvm_set_cpu_caps(void) > kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP); > if (boot_cpu_has(X86_FEATURE_AMD_SSBD)) > kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); > + /* > + * Don't use boot_cpu_has() to check availability of IBT because the > + * feature bit is cleared in boot_cpu_data when ibt=off is applied > + * in host cmdline. I'm not convinced this is a good reason to diverge from the host kernel. E.g. PCID and many other features honor the host setup, I don't see what makes IBT special. LA57 is special because it's entirely reasonable, likely even, for a host to only want to use 48-bit virtual addresses, but still want to let the guest enable LA57. > @@ -4934,6 +4935,14 @@ static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) > > vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ > > + if (kvm_cpu_cap_has(X86_FEATURE_SHSTK)) { > + vmcs_writel(GUEST_SSP, 0); > + vmcs_writel(GUEST_S_CET, 0); > + vmcs_writel(GUEST_INTR_SSP_TABLE, 0); > + } else if (kvm_cpu_cap_has(X86_FEATURE_IBT)) { > + vmcs_writel(GUEST_S_CET, 0); > + } Similar to my comments about MSR interception, I think it would be better to explicitly handle the "common" field. At first glance, code like the above makes it look like IBT is mutually exclusive with SHSTK, e.g. a reader that isn't looking closely could easily miss that both paths write GUEST_S_CET. if (kvm_cpu_cap_has(X86_FEATURE_SHSTK)) { vmcs_writel(GUEST_SSP, 0); vmcs_writel(GUEST_INTR_SSP_TABLE, 0); } if (kvm_cpu_cap_has(X86_FEATURE_IBT) || kvm_cpu_cap_has(X86_FEATURE_SHSTK)) vmcs_writel(GUEST_S_CET, 0);