From: Catalin Marinas <catalin.marinas@arm.com>
To: Yang Shi <yang@os.amperecomputing.com>
Cc: will@kernel.org, anshuman.khandual@arm.com,
scott@os.amperecomputing.com, cl@gentwo.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [v2 PATCH] arm64: mm: force write fault for atomic RMW instructions
Date: Thu, 23 May 2024 18:07:08 +0100 [thread overview]
Message-ID: <Zk93vBqAD3LgmbGb@arm.com> (raw)
In-Reply-To: <20240520165636.802268-1-yang@os.amperecomputing.com>
On Mon, May 20, 2024 at 09:56:36AM -0700, Yang Shi wrote:
> diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h
> index db1aeacd4cd9..1cc73664fc55 100644
> --- a/arch/arm64/include/asm/insn.h
> +++ b/arch/arm64/include/asm/insn.h
> @@ -319,6 +319,7 @@ static __always_inline u32 aarch64_insn_get_##abbr##_value(void) \
> * "-" means "don't care"
> */
> __AARCH64_INSN_FUNCS(class_branch_sys, 0x1c000000, 0x14000000)
> +__AARCH64_INSN_FUNCS(class_atomic, 0x3b200c00, 0x38200000)
While this class includes all atomics that currently require write
permission, there's some unallocated space in this range and we don't
know what future architecture versions may introduce. Unfortunately we
need to check each individual atomic op in this class (not sure what the
overhead will be).
--
Catalin
next prev parent reply other threads:[~2024-05-23 17:07 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-20 16:56 [v2 PATCH] arm64: mm: force write fault for atomic RMW instructions Yang Shi
2024-05-23 17:07 ` Catalin Marinas [this message]
2024-05-23 18:09 ` Christoph Lameter (Ampere)
2024-05-23 19:00 ` Catalin Marinas
2024-05-23 19:43 ` Christoph Lameter (Ampere)
2024-05-23 21:34 ` Catalin Marinas
2024-05-23 22:13 ` Yang Shi
2024-06-03 16:06 ` Catalin Marinas
2024-06-03 20:34 ` Yang Shi
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