From: Andy Shevchenko <andy.shevchenko@gmail.com>
To: Patrick Rudolph <patrick.rudolph@9elements.com>
Cc: Linus Walleij <linus.walleij@linaro.org>,
naresh.solanki@9elements.com, linux-gpio@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] pinctrl: cy8c95x0: Cache muxed registers
Date: Tue, 14 May 2024 08:27:37 +0300 [thread overview]
Message-ID: <ZkL2Sdf0NcqaZRZ4@surfacebook.localdomain> (raw)
In-Reply-To: <20231219125350.4031370-1-patrick.rudolph@9elements.com>
Tue, Dec 19, 2023 at 01:53:49PM +0100, Patrick Rudolph kirjoitti:
> Currently the port specific registers behind the PORTSEL mux aren't
> cached in the regmap and thus the typical setup time for a single pin
> on cy8c9560 is about 200msec on our system. The hotspot is the IRQ
> (un)masking, which causes lots of R/W operations.
>
> Introduce a separate regmap for muxed registers and helper functions
> to use the newly introduced regmap for muxed register access under
> the i2c lock.
>
> With the new cache in place the typical pin setup time is reduced to
> 20msec, making it about 10 times faster. As a side effect the system
> boot time is also reduced by 50%.
Interestingly that you have not Cc'ed me on your patches.
This, btw, a good reinvetion of a wheel which regmap supports already.
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2024-05-14 5:27 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-19 12:53 [PATCH] pinctrl: cy8c95x0: Cache muxed registers Patrick Rudolph
2023-12-20 12:04 ` Linus Walleij
2024-05-14 5:27 ` Andy Shevchenko [this message]
2024-05-14 7:49 ` Linus Walleij
2024-05-14 8:39 ` Patrick Rudolph
2024-05-14 8:51 ` Linus Walleij
2024-05-14 8:55 ` Andy Shevchenko
2024-05-14 8:57 ` Andy Shevchenko
2024-05-14 9:02 ` Mark Brown
2024-05-14 9:23 ` Andy Shevchenko
2024-05-14 9:30 ` Mark Brown
2024-05-14 8:55 ` Mark Brown
2024-05-16 17:03 ` Patrick Rudolph
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