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[188.149.135.220]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-523ba138259sm26690e87.269.2024.05.15.14.48.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 14:48:57 -0700 (PDT) Date: Wed, 15 May 2024 23:48:55 +0200 From: =?iso-8859-1?Q?Ram=F3n?= Nordin Rodriguez To: Parthiban.Veerasooran@microchip.com Cc: andrew@lunn.ch, Pier.Beruto@onsemi.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, horms@kernel.org, saeedm@nvidia.com, anthony.l.nguyen@intel.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, corbet@lwn.net, linux-doc@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, devicetree@vger.kernel.org, Horatiu.Vultur@microchip.com, ruanjinjie@huawei.com, Steen.Hegelund@microchip.com, vladimir.oltean@nxp.com, UNGLinuxDriver@microchip.com, Thorsten.Kummermehr@microchip.com, Selvamani.Rajagopal@onsemi.com, Nicolas.Ferre@microchip.com, benjamin.bigler@bernformulastudent.ch Subject: Re: [PATCH net-next v4 05/12] net: ethernet: oa_tc6: implement error interrupts unmasking Message-ID: References: <708d29de-b54a-40a4-8879-67f6e246f851@lunn.ch> <6e4207cd-2bd5-4f5b-821f-bc87c1296367@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <6e4207cd-2bd5-4f5b-821f-bc87c1296367@microchip.com> On Tue, May 14, 2024 at 04:46:58AM +0000, Parthiban.Veerasooran@microchip.com wrote: > >> Is it doing this in an endless cycle? > > > > Exactly, so what I'm seeing is when the driver livelocks the macphy is > > periodically pulling the irq pin low, the driver clears the interrupt > > and repeat. > If I understand correctly, you are keep on getting interrupt without > indicating anything in the footer?. Are you using LAN8650 Rev.B0 or B1?. > If it is B0 then can you try with Rev.B1 once? > I'll check the footer content, thanks for the tip! All testing has bee done with Rev.B0, we've located a set of B1 chips. So we'll get on resoldering and rerunning the test scenario. R