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AJvYcCUWfT5omDIqKjDbV0OvN6YMM2fTIRTJWByXFx1xhGsMe2aNSzJKOvQe0KDx6xVmCZCMNvtTVqOgmfrg6LJCZLyS17zCFm3mlofn4JqK X-Gm-Message-State: AOJu0YwHhqq9T7VUZ0ApLFMG7BIOlcGH0lzYAn9Svl5hD5sN92vPbSLv GjPvVRn9lXloMKJFnaxJmCe1G66JNQ9m+2E9285K2pFN3RZBrzxmBKkcQ+vvcZEGBRm4L8aaAzO fCQ== X-Google-Smtp-Source: AGHT+IEDBtrDbkovNrhAV/lyqKo9e3I9oLyUsaLll6pFh8+GoJQSddiJzF1Cv5ysvpR9u6J0VFHg196pMTA= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a05:6902:1025:b0:de5:3003:4b83 with SMTP id 3f1490d57ef6-dee4f4fbce6mr1659030276.8.1715868424907; Thu, 16 May 2024 07:07:04 -0700 (PDT) Date: Thu, 16 May 2024 07:07:03 -0700 In-Reply-To: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240507061802.20184-1-yan.y.zhao@intel.com> <20240507061924.20251-1-yan.y.zhao@intel.com> Message-ID: Subject: Re: [PATCH 1/5] x86/pat: Let pat_pfn_immune_to_uc_mtrr() check MTRR for untracked PAT range From: Sean Christopherson To: Kevin Tian Cc: Yan Y Zhao , "kvm@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "x86@kernel.org" , "alex.williamson@redhat.com" , "jgg@nvidia.com" , "iommu@lists.linux.dev" , "pbonzini@redhat.com" , "dave.hansen@linux.intel.com" , "luto@kernel.org" , "peterz@infradead.org" , "tglx@linutronix.de" , "mingo@redhat.com" , "bp@alien8.de" , "hpa@zytor.com" , "corbet@lwn.net" , "joro@8bytes.org" , "will@kernel.org" , "robin.murphy@arm.com" , "baolu.lu@linux.intel.com" , Yi L Liu , Tom Lendacky Content-Type: text/plain; charset="us-ascii" +Tom On Thu, May 16, 2024, Kevin Tian wrote: > > From: Zhao, Yan Y > > Sent: Tuesday, May 7, 2024 5:13 PM > > > > On Tue, May 07, 2024 at 04:26:37PM +0800, Tian, Kevin wrote: > > > > From: Zhao, Yan Y > > > > Sent: Tuesday, May 7, 2024 2:19 PM > > > > > > > > @@ -705,7 +705,17 @@ static enum page_cache_mode > > > > lookup_memtype(u64 paddr) > > > > */ > > > > bool pat_pfn_immune_to_uc_mtrr(unsigned long pfn) > > > > { > > > > - enum page_cache_mode cm = lookup_memtype(PFN_PHYS(pfn)); > > > > + u64 paddr = PFN_PHYS(pfn); > > > > + enum page_cache_mode cm; > > > > + > > > > + /* > > > > + * Check MTRR type for untracked pat range since lookup_memtype() > > > > always > > > > + * returns WB for this range. > > > > + */ > > > > + if (x86_platform.is_untracked_pat_range(paddr, paddr + PAGE_SIZE)) > > > > + cm = pat_x_mtrr_type(paddr, paddr + PAGE_SIZE, > > > > _PAGE_CACHE_MODE_WB); > > > > > > doing so violates the name of this function. The PAT of the untracked > > > range is still WB and not immune to UC MTRR. > > Right. > > Do you think we can rename this function to something like > > pfn_of_uncachable_effective_memory_type() and make it work under > > !pat_enabled() too? > > let's hear from x86/kvm maintainers for their opinions. > > My gut-feeling is that kvm_is_mmio_pfn() might be moved into the > x86 core as the logic there has nothing specific to kvm itself. Also > naming-wise it doesn't really matter whether the pfn is mmio. The > real point is to find the uncacheble memtype in the primary mmu > and then follow it in KVM. Yeaaaah, we've got an existing problem there. When AMD's SME is enabled, KVM uses kvm_is_mmio_pfn() to determine whether or not to map memory into the guest as encrypted or plain text. I.e. KVM really does try to use this helper to detect MMIO vs. RAM. I highly doubt that actually works in all setups. For SME, it seems like the best approach would be grab the C-Bit from the host page tables, similar to how KVM uses host_pfn_mapping_level(). SME aside, I don't have objection to moving kvm_is_mmio_pfn() out of KVM. > from that point probably a pfn_memtype_uncacheable() reads clearer. or even just pfn_is_memtype_uc()?