From: Andrea Parri <parri.andrea@gmail.com>
To: Alexandre Ghiti <alexghiti@rivosinc.com>
Cc: Jonathan Corbet <corbet@lwn.net>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>, Will Deacon <will@kernel.org>,
Waiman Long <longman@redhat.com>,
Boqun Feng <boqun.feng@gmail.com>, Arnd Bergmann <arnd@arndb.de>,
Leonardo Bras <leobras@redhat.com>, Guo Ren <guoren@kernel.org>,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-arch@vger.kernel.org
Subject: Re: [PATCH 4/7] riscv: Implement xchg8/16() using Zabha
Date: Tue, 28 May 2024 20:00:26 +0200 [thread overview]
Message-ID: <ZlYbupL5XgzgA0MX@andrea> (raw)
In-Reply-To: <20240528151052.313031-5-alexghiti@rivosinc.com>
> -#define __arch_xchg_masked(prepend, append, r, p, n) \
> +#define __arch_xchg_masked(swap_sfx, prepend, append, r, p, n) \
This actually indicates a problem in the current (aka, no Zabha)
implementation: without your series, xchg16() gets mapped to
lr.w a2,(a3)
and a1,a2,a5
or a1,a1,a4
sc.w a1,a1,(a3)
bnez a1,43c <.L0^B1>
which is clearly wrong... (other "fully-ordered LR/SC sequences"
instead follow the mapping
lr.w a2,(a3)
and a1,a2,a5
or a1,a1,a4
sc.w.rl a1,a1,(a3)
bnez a1,43c <.L0^B1>
fence rw,rw )
A similar consideration for xchg8().
Andrea
next prev parent reply other threads:[~2024-05-28 18:00 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-28 15:10 [PATCH 0/7] Zacas/Zabha support and qspinlocks Alexandre Ghiti
2024-05-28 15:10 ` [PATCH 1/7] riscv: Implement cmpxchg32/64() using Zacas Alexandre Ghiti
2024-05-28 15:34 ` Conor Dooley
2024-05-29 12:20 ` Alexandre Ghiti
2024-05-30 14:43 ` Conor Dooley
2024-05-28 18:16 ` Andrea Parri
2024-05-28 15:10 ` [PATCH 2/7] riscv: Implement cmpxchg8/16() using Zabha Alexandre Ghiti
2024-05-28 19:31 ` Nathan Chancellor
2024-05-29 12:49 ` Alexandre Ghiti
2024-05-29 15:57 ` Nathan Chancellor
2024-06-03 15:31 ` Alexandre Ghiti
2024-05-28 23:54 ` Andrea Parri
2024-05-29 12:29 ` Alexandre Ghiti
2024-05-29 12:55 ` Alexandre Ghiti
2024-05-28 15:10 ` [PATCH 3/7] riscv: Implement arch_cmpxchg128() using Zacas Alexandre Ghiti
2024-05-28 15:10 ` [PATCH 4/7] riscv: Implement xchg8/16() using Zabha Alexandre Ghiti
2024-05-28 15:22 ` Conor Dooley
2024-05-29 6:15 ` Alexandre Ghiti
2024-05-28 18:00 ` Andrea Parri [this message]
2024-05-29 8:04 ` Alexandre Ghiti
2024-05-28 15:10 ` [PATCH 5/7] asm-generic: ticket-lock: Reuse arch_spinlock_t of qspinlock Alexandre Ghiti
2024-05-28 15:10 ` [PATCH 6/7] asm-generic: ticket-lock: Add separate ticket-lock.h Alexandre Ghiti
2024-05-28 15:10 ` [PATCH 7/7] riscv: Add qspinlock support based on Zabha extension Alexandre Ghiti
2024-05-29 0:55 ` Andrea Parri
2024-05-31 13:37 ` Alexandre Ghiti
2024-05-31 15:52 ` Andrea Parri
2024-06-01 6:18 ` Guo Ren
2024-06-03 0:41 ` Andrea Parri
2024-05-29 9:23 ` Guo Ren
2024-05-29 13:03 ` Alexandre Ghiti
2024-05-30 1:54 ` Guo Ren
2024-05-30 5:30 ` Alexandre Ghiti
2024-05-31 1:57 ` Guo Ren
2024-05-31 6:22 ` Alexandre Ghiti
2024-05-31 6:42 ` Guo Ren
2024-06-03 9:21 ` Alexandre Ghiti
2024-06-03 11:11 ` Guo Ren
2024-05-31 13:10 ` Guo Ren
2024-06-03 9:49 ` Alexandre Ghiti
2024-06-03 11:28 ` Guo Ren
2024-06-03 11:34 ` Alexandre Ghiti
2024-06-03 11:44 ` Guo Ren
2024-06-03 11:49 ` Alexandre Ghiti
2024-06-03 11:57 ` Guo Ren
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