Re: [PATCH 1/5] x86/pat: Let pat_pfn_immune_to_uc_mtrr() check MTRR for untracked PAT range

Yan Zhao
2024-05-07T09:13:28Z

On Tue, May 07, 2024 at 04:26:37PM +0800, Tian, Kevin wrote:
> > From: Zhao, Yan Y <yan.y.zhao@intel.com>
> > Sent: Tuesday, May 7, 2024 2:19 PM
> >
> > However, lookup_memtype() defaults to returning WB for PFNs within the
> > untracked PAT range, regardless of their actual MTRR type. This behavior
> > could lead KVM to misclassify the PFN as non-MMIO, permitting cacheable
> > guest access. Such access might result in MCE on certain platforms, (e.g.
> > clflush on VGA range (0xA0000-0xBFFFF) triggers MCE on some platforms).
>
> the VGA range is not exposed to any guest today. So is it just trying to
> fix a theoretical problem?

Yes. Not sure if VGA range is allowed to be exposed to guest in future, given
we have VFIO variant drivers.

>
> > @@ -705,7 +705,17 @@ static enum page_cache_mode
> > lookup_memtype(u64 paddr)
> > */
> > bool pat_pfn_immune_to_uc_mtrr(unsigned long pfn)
> > {
> > - enum page_cache_mode cm = lookup_memtype(PFN_PHYS(pfn));
> > + u64 paddr = PFN_PHYS(pfn);
> > + enum page_cache_mode cm;
> > +
> > + /*
> > + * Check MTRR type for untracked pat range since lookup_memtype()
> > always
> > + * returns WB for this range.
> > + */
> > + if (x86_platform.is_untracked_pat_range(paddr, paddr + PAGE_SIZE))
> > + cm = pat_x_mtrr_type(paddr, paddr + PAGE_SIZE,
> > _PAGE_CACHE_MODE_WB);
>
> doing so violates the name of this function. The PAT of the untracked
> range is still WB and not immune to UC MTRR.
Right.
Do you think we can rename this function to something like
pfn_of_uncachable_effective_memory_type() and make it work under !pat_enabled()
too?

>
> > + else
> > + cm = lookup_memtype(paddr);
> >
> > return cm == _PAGE_CACHE_MODE_UC ||
> > cm == _PAGE_CACHE_MODE_UC_MINUS ||
>