Re: [PATCH 4/5] vfio/type1: Flush CPU caches on DMA pages in non-coherent domains

Yan Zhao
2024-05-22T03:34:40Z

On Tue, May 21, 2024 at 12:19:45PM -0600, Alex Williamson wrote:
> On Tue, 21 May 2024 13:34:00 -0300
> Jason Gunthorpe <jgg@nvidia.com> wrote:
>
> > On Tue, May 21, 2024 at 10:21:23AM -0600, Alex Williamson wrote:

> Intel folks might be able to comment on the performance hit relative to
> iGPU assignment of denying the device the ability to use no-snoop
> transactions (assuming the device control bit is actually honored).
I don't have direct data for iGPU assignment. But I have a reference
data regarding to virtio GPU.

When backend GPU is iGPU for a virtio GPU, follow non-coherent path could
increase performance up to 20%+ for some platforms.

> The latency of flushing caches on touching no-snoop enable might be
> prohibitive in the latter case. Thanks,