* [PATCH] RISC-V: fix vector insn load/store width mask
@ 2024-06-06 18:28 Jesse Taube
2024-06-06 18:59 ` Charlie Jenkins
2024-06-26 14:21 ` patchwork-bot+linux-riscv
0 siblings, 2 replies; 3+ messages in thread
From: Jesse Taube @ 2024-06-06 18:28 UTC (permalink / raw)
To: linux-riscv
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley, Nam Cao,
Sami Tolvanen, Charlie Jenkins, Andy Chiu, Jesse Taube,
linux-kernel
RVFDQ_FL_FS_WIDTH_MASK should be 3 bits [14-12], shifted down by 12 bits.
Replace GENMASK(3, 0) with GENMASK(2, 0).
Fixes: cd054837243b ("riscv: Allocate user's vector context in the first-use trap")
Signed-off-by: Jesse Taube <jesse@rivosinc.com>
---
arch/riscv/include/asm/insn.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h
index 06e439eeef9a..09fde95a5e8f 100644
--- a/arch/riscv/include/asm/insn.h
+++ b/arch/riscv/include/asm/insn.h
@@ -145,7 +145,7 @@
/* parts of opcode for RVF, RVD and RVQ */
#define RVFDQ_FL_FS_WIDTH_OFF 12
-#define RVFDQ_FL_FS_WIDTH_MASK GENMASK(3, 0)
+#define RVFDQ_FL_FS_WIDTH_MASK GENMASK(2, 0)
#define RVFDQ_FL_FS_WIDTH_W 2
#define RVFDQ_FL_FS_WIDTH_D 3
#define RVFDQ_LS_FS_WIDTH_Q 4
--
2.43.0
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] RISC-V: fix vector insn load/store width mask
2024-06-06 18:28 [PATCH] RISC-V: fix vector insn load/store width mask Jesse Taube
@ 2024-06-06 18:59 ` Charlie Jenkins
2024-06-26 14:21 ` patchwork-bot+linux-riscv
1 sibling, 0 replies; 3+ messages in thread
From: Charlie Jenkins @ 2024-06-06 18:59 UTC (permalink / raw)
To: Jesse Taube
Cc: linux-riscv, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Conor Dooley, Nam Cao, Sami Tolvanen, Andy Chiu, linux-kernel
On Thu, Jun 06, 2024 at 02:28:00PM -0400, Jesse Taube wrote:
> RVFDQ_FL_FS_WIDTH_MASK should be 3 bits [14-12], shifted down by 12 bits.
> Replace GENMASK(3, 0) with GENMASK(2, 0).
>
> Fixes: cd054837243b ("riscv: Allocate user's vector context in the first-use trap")
> Signed-off-by: Jesse Taube <jesse@rivosinc.com>
> ---
> arch/riscv/include/asm/insn.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h
> index 06e439eeef9a..09fde95a5e8f 100644
> --- a/arch/riscv/include/asm/insn.h
> +++ b/arch/riscv/include/asm/insn.h
> @@ -145,7 +145,7 @@
>
> /* parts of opcode for RVF, RVD and RVQ */
> #define RVFDQ_FL_FS_WIDTH_OFF 12
> -#define RVFDQ_FL_FS_WIDTH_MASK GENMASK(3, 0)
> +#define RVFDQ_FL_FS_WIDTH_MASK GENMASK(2, 0)
> #define RVFDQ_FL_FS_WIDTH_W 2
> #define RVFDQ_FL_FS_WIDTH_D 3
> #define RVFDQ_LS_FS_WIDTH_Q 4
> --
> 2.43.0
>
Thanks!
Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] RISC-V: fix vector insn load/store width mask
2024-06-06 18:28 [PATCH] RISC-V: fix vector insn load/store width mask Jesse Taube
2024-06-06 18:59 ` Charlie Jenkins
@ 2024-06-26 14:21 ` patchwork-bot+linux-riscv
1 sibling, 0 replies; 3+ messages in thread
From: patchwork-bot+linux-riscv @ 2024-06-26 14:21 UTC (permalink / raw)
To: Jesse Taube
Cc: linux-riscv, paul.walmsley, palmer, aou, conor.dooley, namcaov,
samitolvanen, charlie, andy.chiu, linux-kernel
Hello:
This patch was applied to riscv/linux.git (fixes)
by Palmer Dabbelt <palmer@rivosinc.com>:
On Thu, 6 Jun 2024 14:28:00 -0400 you wrote:
> RVFDQ_FL_FS_WIDTH_MASK should be 3 bits [14-12], shifted down by 12 bits.
> Replace GENMASK(3, 0) with GENMASK(2, 0).
>
> Fixes: cd054837243b ("riscv: Allocate user's vector context in the first-use trap")
> Signed-off-by: Jesse Taube <jesse@rivosinc.com>
> ---
> arch/riscv/include/asm/insn.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Here is the summary with links:
- RISC-V: fix vector insn load/store width mask
https://git.kernel.org/riscv/c/04a2aef59cfe
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
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2024-06-06 18:28 [PATCH] RISC-V: fix vector insn load/store width mask Jesse Taube
2024-06-06 18:59 ` Charlie Jenkins
2024-06-26 14:21 ` patchwork-bot+linux-riscv
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