[PATCH RESEND v5 1/3] riscv: cacheinfo: remove the useless input parameter (node) of ci_leaf_init()

[PATCH RESEND v5 1/3] riscv: cacheinfo: remove the useless input parameter (node) of ci_leaf_init()

[Yunhui Cui]

ci_leaf_init() is a declared static function. The implementation of the
function body and the caller do not use the parameter (struct device_node
*node) input parameter, so remove it.

Fixes: 6a24915145c9 ("Revert "riscv: Set more data to cacheinfo"")
Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
Reviewed-by: Jeremy Linton <jeremy.linton@arm.com>
Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
---
 arch/riscv/kernel/cacheinfo.c | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c
index 09e9b88110d1..30a6878287ad 100644
--- a/arch/riscv/kernel/cacheinfo.c
+++ b/arch/riscv/kernel/cacheinfo.c
@@ -64,7 +64,6 @@ uintptr_t get_cache_geometry(u32 level, enum cache_type type)
 }
 
 static void ci_leaf_init(struct cacheinfo *this_leaf,
-			 struct device_node *node,
 			 enum cache_type type, unsigned int level)
 {
 	this_leaf->level = level;
@@ -80,11 +79,11 @@ int populate_cache_leaves(unsigned int cpu)
 	int levels = 1, level = 1;
 
 	if (of_property_read_bool(np, "cache-size"))
-		ci_leaf_init(this_leaf++, np, CACHE_TYPE_UNIFIED, level);
+		ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
 	if (of_property_read_bool(np, "i-cache-size"))
-		ci_leaf_init(this_leaf++, np, CACHE_TYPE_INST, level);
+		ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
 	if (of_property_read_bool(np, "d-cache-size"))
-		ci_leaf_init(this_leaf++, np, CACHE_TYPE_DATA, level);
+		ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
 
 	prev = np;
 	while ((np = of_find_next_cache_node(np))) {
@@ -97,11 +96,11 @@ int populate_cache_leaves(unsigned int cpu)
 		if (level <= levels)
 			break;
 		if (of_property_read_bool(np, "cache-size"))
-			ci_leaf_init(this_leaf++, np, CACHE_TYPE_UNIFIED, level);
+			ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
 		if (of_property_read_bool(np, "i-cache-size"))
-			ci_leaf_init(this_leaf++, np, CACHE_TYPE_INST, level);
+			ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
 		if (of_property_read_bool(np, "d-cache-size"))
-			ci_leaf_init(this_leaf++, np, CACHE_TYPE_DATA, level);
+			ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
 		levels = level;
 	}
 	of_node_put(np);
-- 
2.20.1

[PATCH RESEND v5 2/3] riscv: cacheinfo: initialize cacheinfo's level and type from ACPI PPTT

[Yunhui Cui]

Before cacheinfo can be built correctly, we need to initialize level
and type. Since RISC-V currently does not have a register group that
describes cache-related attributes like ARM64, we cannot obtain them
directly, so now we obtain cache leaves from the ACPI PPTT table
(acpi_get_cache_info()) and set the cache type through split_levels.

Suggested-by: Jeremy Linton <jeremy.linton@arm.com>
Suggested-by: Sudeep Holla <sudeep.holla@arm.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Jeremy Linton <jeremy.linton@arm.com>
Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
---
 arch/riscv/kernel/cacheinfo.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c
index 30a6878287ad..d6c108c50cba 100644
--- a/arch/riscv/kernel/cacheinfo.c
+++ b/arch/riscv/kernel/cacheinfo.c
@@ -3,6 +3,7 @@
  * Copyright (C) 2017 SiFive
  */
 
+#include <linux/acpi.h>
 #include <linux/cpu.h>
 #include <linux/of.h>
 #include <asm/cacheinfo.h>
@@ -78,6 +79,27 @@ int populate_cache_leaves(unsigned int cpu)
 	struct device_node *prev = NULL;
 	int levels = 1, level = 1;
 
+	if (!acpi_disabled) {
+		int ret, fw_levels, split_levels;
+
+		ret = acpi_get_cache_info(cpu, &fw_levels, &split_levels);
+		if (ret)
+			return ret;
+
+		BUG_ON((split_levels > fw_levels) ||
+		       (split_levels + fw_levels > this_cpu_ci->num_leaves));
+
+		for (; level <= this_cpu_ci->num_levels; level++) {
+			if (level <= split_levels) {
+				ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
+				ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
+			} else {
+				ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
+			}
+		}
+		return 0;
+	}
+
 	if (of_property_read_bool(np, "cache-size"))
 		ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
 	if (of_property_read_bool(np, "i-cache-size"))
-- 
2.20.1

[PATCH RESEND v5 3/3] RISC-V: Select ACPI PPTT drivers

[Yunhui Cui]

After adding ACPI support to populate_cache_leaves(), RISC-V can build
cacheinfo through the ACPI PPTT table, thus enabling the ACPI_PPTT
configuration.

Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
Reviewed-by: Jeremy Linton <jeremy.linton@arm.com>
Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
---
 arch/riscv/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index f961449ca077..a9ebecd72052 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -14,6 +14,7 @@ config RISCV
 	def_bool y
 	select ACPI_GENERIC_GSI if ACPI
 	select ACPI_REDUCED_HARDWARE_ONLY if ACPI
+	select ACPI_PPTT if ACPI
 	select ARCH_DMA_DEFAULT_COHERENT
 	select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
 	select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
-- 
2.20.1

Re: [PATCH RESEND v5 3/3] RISC-V: Select ACPI PPTT drivers

[yunhui cui]

Hi Palmer,

Gentle ping ...

On Thu, May 23, 2024 at 7:13 PM Yunhui Cui <cuiyunhui@bytedance.com> wrote:
>
> After adding ACPI support to populate_cache_leaves(), RISC-V can build
> cacheinfo through the ACPI PPTT table, thus enabling the ACPI_PPTT
> configuration.
>
> Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
> Reviewed-by: Jeremy Linton <jeremy.linton@arm.com>
> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
> ---
>  arch/riscv/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index f961449ca077..a9ebecd72052 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -14,6 +14,7 @@ config RISCV
>         def_bool y
>         select ACPI_GENERIC_GSI if ACPI
>         select ACPI_REDUCED_HARDWARE_ONLY if ACPI
> +       select ACPI_PPTT if ACPI
>         select ARCH_DMA_DEFAULT_COHERENT
>         select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
>         select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
> --
> 2.20.1
>

Thanks,
Yunhui

Re: [PATCH RESEND v5 3/3] RISC-V: Select ACPI PPTT drivers

[yunhui cui]

Hi Sunilvl,


On Mon, May 27, 2024 at 8:51 PM yunhui cui <cuiyunhui@bytedance.com> wrote:
>
> Hi Palmer,
>
> Gentle ping ...
>
> On Thu, May 23, 2024 at 7:13 PM Yunhui Cui <cuiyunhui@bytedance.com> wrote:
> >
> > After adding ACPI support to populate_cache_leaves(), RISC-V can build
> > cacheinfo through the ACPI PPTT table, thus enabling the ACPI_PPTT
> > configuration.
> >
> > Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
> > Reviewed-by: Jeremy Linton <jeremy.linton@arm.com>
> > Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
> > ---
> >  arch/riscv/Kconfig | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index f961449ca077..a9ebecd72052 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -14,6 +14,7 @@ config RISCV
> >         def_bool y
> >         select ACPI_GENERIC_GSI if ACPI
> >         select ACPI_REDUCED_HARDWARE_ONLY if ACPI
> > +       select ACPI_PPTT if ACPI
> >         select ARCH_DMA_DEFAULT_COHERENT
> >         select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
> >         select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
> > --
> > 2.20.1
> >
>
> Thanks,
> Yunhui

Could you please review or ack this patchset again? Palmer did not respond.

Link:
https://lore.kernel.org/linux-riscv/20240523111322.19243-3-cuiyunhui@bytedance.com/T/

Thanks,
Yunhui

Re: [PATCH RESEND v5 3/3] RISC-V: Select ACPI PPTT drivers

[Sunil V L]

Hi Yunhui,

On Fri, Jun 07, 2024 at 04:44:36PM +0800, yunhui cui wrote:
> Hi Sunilvl,
> 
> 
> On Mon, May 27, 2024 at 8:51 PM yunhui cui <cuiyunhui@bytedance.com> wrote:
> >
> > Hi Palmer,
> >
> > Gentle ping ...
> >
> > On Thu, May 23, 2024 at 7:13 PM Yunhui Cui <cuiyunhui@bytedance.com> wrote:
> > >
> > > After adding ACPI support to populate_cache_leaves(), RISC-V can build
> > > cacheinfo through the ACPI PPTT table, thus enabling the ACPI_PPTT
> > > configuration.
> > >
> > > Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
> > > Reviewed-by: Jeremy Linton <jeremy.linton@arm.com>
> > > Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
> > > ---
> > >  arch/riscv/Kconfig | 1 +
> > >  1 file changed, 1 insertion(+)
> > >
> > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > > index f961449ca077..a9ebecd72052 100644
> > > --- a/arch/riscv/Kconfig
> > > +++ b/arch/riscv/Kconfig
> > > @@ -14,6 +14,7 @@ config RISCV
> > >         def_bool y
> > >         select ACPI_GENERIC_GSI if ACPI
> > >         select ACPI_REDUCED_HARDWARE_ONLY if ACPI
> > > +       select ACPI_PPTT if ACPI
NIT: I would add this prior to ACPI_REDUCED_HARDWARE_ONLY.

> > >         select ARCH_DMA_DEFAULT_COHERENT
> > >         select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
> > >         select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
> > > --
> > > 2.20.1
> > >
> >
> > Thanks,
> > Yunhui
> 
> Could you please review or ack this patchset again? Palmer did not respond.
> 
> Link:
> https://lore.kernel.org/linux-riscv/20240523111322.19243-3-cuiyunhui@bytedance.com/T/
> 
My bad, I was under the impression that I had Acked already. The series
looks good to me except the nit above.

Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>

Thanks,
Sunil

Re: [External] Re: [PATCH RESEND v5 3/3] RISC-V: Select ACPI PPTT drivers

[yunhui cui]

Hi Sunil,

On Fri, Jun 7, 2024 at 7:01 PM Sunil V L <sunilvl@ventanamicro.com> wrote:
>
> Hi Yunhui,
>
> On Fri, Jun 07, 2024 at 04:44:36PM +0800, yunhui cui wrote:
> > Hi Sunilvl,
> >
> >
> > On Mon, May 27, 2024 at 8:51 PM yunhui cui <cuiyunhui@bytedance.com> wrote:
> > >
> > > Hi Palmer,
> > >
> > > Gentle ping ...
> > >
> > > On Thu, May 23, 2024 at 7:13 PM Yunhui Cui <cuiyunhui@bytedance.com> wrote:
> > > >
> > > > After adding ACPI support to populate_cache_leaves(), RISC-V can build
> > > > cacheinfo through the ACPI PPTT table, thus enabling the ACPI_PPTT
> > > > configuration.
> > > >
> > > > Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
> > > > Reviewed-by: Jeremy Linton <jeremy.linton@arm.com>
> > > > Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
> > > > ---
> > > >  arch/riscv/Kconfig | 1 +
> > > >  1 file changed, 1 insertion(+)
> > > >
> > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > > > index f961449ca077..a9ebecd72052 100644
> > > > --- a/arch/riscv/Kconfig
> > > > +++ b/arch/riscv/Kconfig
> > > > @@ -14,6 +14,7 @@ config RISCV
> > > >         def_bool y
> > > >         select ACPI_GENERIC_GSI if ACPI
> > > >         select ACPI_REDUCED_HARDWARE_ONLY if ACPI
> > > > +       select ACPI_PPTT if ACPI
> NIT: I would add this prior to ACPI_REDUCED_HARDWARE_ONLY.

Okay, I will update it on v6.

>
> > > >         select ARCH_DMA_DEFAULT_COHERENT
> > > >         select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
> > > >         select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
> > > > --
> > > > 2.20.1
> > > >
> > >
> > > Thanks,
> > > Yunhui
> >
> > Could you please review or ack this patchset again? Palmer did not respond.
> >
> > Link:
> > https://lore.kernel.org/linux-riscv/20240523111322.19243-3-cuiyunhui@bytedance.com/T/
> >
> My bad, I was under the impression that I had Acked already. The series
> looks good to me except the nit above.
>
> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
>
> Thanks,
> Sunil

Thanks,
Yunhui