Re: [PATCH v2 0/3] Add support for the Mobileye EyeQ6H SoC

[Thomas Bogendoerfer <tsbogend@alpha.franken.de>]

On Mon, Jun 10, 2024 at 04:47:47PM +0200, Gregory CLEMENT wrote:
> > Following the support of the EyeQ5 SoC, this series adds the initial
> > support for a newer SoC, the EyeQ6H.
> >
> > The EyeQ6H (or "High") from Mobileye is still based on the MIPS I6500
> > architecture as the EyeQ5. The 2 clusters of this SoC contain 4 cores
> > each, which are capable of running 4 threads per core. Besides this,
> > it features multiple controllers such as the classic UART, high-speed
> > I2C, SPI, as well as CAN-FD, PCIe Gen4, Octal/Quad SPI Flash
> > interface, Gigabit Ethernet, MIPI CSI-2, MIPI DSI, and eMMC 5.1. It
> > also includes a Hardware Security Module, Functional Safety Hardware,
> > and video encoders, among other features.
> >
> > For now, this series just adds initial support with UART and Pinctrl
> > support. Another current limitation pointed out in patch 3 is that
> > only one CPU is actually running. This limitation will be solved with
> > upcoming series.
> >
> > The main change in this new version is the use of the new way to name
> > the clock nodes.
> 
> I sent this second version a month ago and the first version even before
> that, and I still haven't received any feedback from your side. Does it
> mean that you will merge it?

I will this week. The second version came around merge window, so I didn't
want to include it.

Thomas.

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