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Date: Wed, 12 Jun 2024 10:21:54 +0100
From: Catalin Marinas <catalin.marinas@arm.com>
To: Fred Griffoul <fgriffo@amazon.co.uk>
Cc: griffoul@gmail.com, kernel test robot <lkp@intel.com>,
	Will Deacon <will@kernel.org>,
	Alex Williamson <alex.williamson@redhat.com>,
	Waiman Long <longman@redhat.com>,
	Zefan Li <lizefan.x@bytedance.com>, Tejun Heo <tj@kernel.org>,
	Johannes Weiner <hannes@cmpxchg.org>,
	Mark Rutland <mark.rutland@arm.com>, Marc Zyngier <maz@kernel.org>,
	Oliver Upton <oliver.upton@linux.dev>,
	Mark Brown <broonie@kernel.org>, Ard Biesheuvel <ardb@kernel.org>,
	Joey Gouly <joey.gouly@arm.com>,
	Ryan Roberts <ryan.roberts@arm.com>,
	Jeremy Linton <jeremy.linton@arm.com>,
	Jason Gunthorpe <jgg@ziepe.ca>, Yi Liu <yi.l.liu@intel.com>,
	Kevin Tian <kevin.tian@intel.com>,
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	Ankit Agrawal <ankita@nvidia.com>,
	Reinette Chatre <reinette.chatre@intel.com>,
	Ye Bin <yebin10@huawei.com>, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
	cgroups@vger.kernel.org
Subject: Re: [PATCH v6 1/2] cgroup/cpuset: export cpuset_cpus_allowed()
Message-ID: <Zmlosj-Fmsoq1AiU@arm.com>
References: <20240611174430.90787-1-fgriffo@amazon.co.uk>
 <20240611174430.90787-2-fgriffo@amazon.co.uk>
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In-Reply-To: <20240611174430.90787-2-fgriffo@amazon.co.uk>

On Tue, Jun 11, 2024 at 05:44:24PM +0000, Fred Griffoul wrote:
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index 56583677c1f2..2f1de6343bee 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -127,6 +127,7 @@ static bool __read_mostly allow_mismatched_32bit_el0;
>   * seen at least one CPU capable of 32-bit EL0.
>   */
>  DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0);
> +EXPORT_SYMBOL_GPL(arm64_mismatched_32bit_el0);
>  
>  /*
>   * Mask of CPUs supporting 32-bit EL0.
> @@ -1614,6 +1615,7 @@ const struct cpumask *system_32bit_el0_cpumask(void)
>  
>  	return cpu_possible_mask;
>  }
> +EXPORT_SYMBOL_GPL(system_32bit_el0_cpumask);

For the arm64 bits:

Acked-by: Catalin Marinas <catalin.marinas@arm.com>