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X-CSE-ConnectionGUID: 6bNzoYPURTSXRQlE22h7FQ== X-CSE-MsgGUID: iU0nJEc5QgmQ2DMp7kf4vw== X-IronPort-AV: E=McAfee;i="6700,10204,11101"; a="40415414" X-IronPort-AV: E=Sophos;i="6.08,234,1712646000"; d="scan'208";a="40415414" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2024 12:55:06 -0700 X-CSE-ConnectionGUID: HMUvc0fjSMur9HBLGzBIug== X-CSE-MsgGUID: PPNktQK9SR6WqHxi1uZyLg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,234,1712646000"; d="scan'208";a="39845552" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 12 Jun 2024 12:55:02 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 12 Jun 2024 22:55:01 +0300 Date: Wed, 12 Jun 2024 22:55:01 +0300 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: =?iso-8859-1?Q?Andr=E9?= Almeida Cc: dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, kernel-dev@igalia.com, alexander.deucher@amd.com, christian.koenig@amd.com, Simon Ser , Pekka Paalanen , daniel@ffwll.ch, Daniel Stone , 'Marek =?utf-8?B?T2zFocOhayc=?= , Dave Airlie , Xaver Hugl , Joshua Ashton , Michel =?iso-8859-1?Q?D=E4nzer?= Subject: Re: [PATCH v5 2/3] drm: Allow drivers to choose plane types to async flip Message-ID: References: <20240612193713.167448-1-andrealmeid@igalia.com> <20240612193713.167448-3-andrealmeid@igalia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240612193713.167448-3-andrealmeid@igalia.com> X-Patchwork-Hint: comment On Wed, Jun 12, 2024 at 04:37:12PM -0300, André Almeida wrote: > Different planes may have different capabilities of doing async flips, > so create a field to let drivers allow async flip per plane type. > > Signed-off-by: André Almeida > --- > drivers/gpu/drm/drm_atomic_uapi.c | 4 ++-- > drivers/gpu/drm/drm_plane.c | 3 +++ > include/drm/drm_plane.h | 5 +++++ > 3 files changed, 10 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c > index 2e1d9391febe..dd4b1578f141 100644 > --- a/drivers/gpu/drm/drm_atomic_uapi.c > +++ b/drivers/gpu/drm/drm_atomic_uapi.c > @@ -1079,9 +1079,9 @@ int drm_atomic_set_property(struct drm_atomic_state *state, > break; > } > > - if (async_flip && plane_state->plane->type != DRM_PLANE_TYPE_PRIMARY) { > + if (async_flip && !plane_state->plane->async_flip) { You alreayd have 'plane', no need to dog it out again. > drm_dbg_atomic(prop->dev, > - "[OBJECT:%d] Only primary planes can be changed during async flip\n", > + "[OBJECT:%d] This type of plane cannot be changed during async flip\n", > obj->id); "[PLANE:%d:%s] does not support async flips" or something like it would make more sense to me. > ret = -EINVAL; > break; > diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c > index 57662a1fd345..bbcec3940636 100644 > --- a/drivers/gpu/drm/drm_plane.c > +++ b/drivers/gpu/drm/drm_plane.c > @@ -385,6 +385,9 @@ static int __drm_universal_plane_init(struct drm_device *dev, > > drm_modeset_lock_init(&plane->mutex); > > + if (type == DRM_PLANE_TYPE_PRIMARY) > + plane->async_flip = true; Setting that would be the job of the driver. You could probably just nuke mode_config.async_page_flip and replace it fully with plane.async_flip checks. > + > plane->base.properties = &plane->properties; > plane->dev = dev; > plane->funcs = funcs; > diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h > index 9507542121fa..0bebc72af5c3 100644 > --- a/include/drm/drm_plane.h > +++ b/include/drm/drm_plane.h > @@ -786,6 +786,11 @@ struct drm_plane { > * @kmsg_panic: Used to register a panic notifier for this plane > */ > struct kmsg_dumper kmsg_panic; > + > + /** > + * @async_flip: indicates if a plane can do async flips > + */ > + bool async_flip; > }; > > #define obj_to_plane(x) container_of(x, struct drm_plane, base) > -- > 2.45.2 -- Ville Syrjälä Intel