From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32D65195F03 for ; Fri, 14 Jun 2024 12:20:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718367634; cv=none; b=bPwf8lWjemkc98O+PTZ4JDogfKzB0h30tu372/SFTL1o1eO4YQf+iBS39CUnoMAYz5FHN2BN+SAi007CrpGvMR095IpF1rRHDghkdIS9HzZtpCF8Kq+lmWfS5TRYLHUcQhfLSlHUfRvin1NGEdZfhBKvgLIadtgQmrjVdh9ySqo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718367634; c=relaxed/simple; bh=rF8IQJXE+F+fPTThN+RuBNY1i5eZMY2Xeb1eGXWtmso=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=dvKni18TiRunzXDLh1eQOccc4fKMACKUWU939cw/Hm6YC+IPnBIWbJDReHruhE8IH6MJg0gatAF4rdJCmdLJvf+U25BgdFoJFQzcTJxdEB9JvrqFF/6WsSU5MMRzU4sgDHRf7QscmEANAEOEm/dFbuxw2i1XySIgkFIC00w39NM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 91235C2BD10; Fri, 14 Jun 2024 12:20:32 +0000 (UTC) Date: Fri, 14 Jun 2024 13:20:30 +0100 From: Catalin Marinas To: Yang Shi Cc: will@kernel.org, anshuman.khandual@arm.com, scott@os.amperecomputing.com, cl@gentwo.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [v4 PATCH] arm64: mm: force write fault for atomic RMW instructions Message-ID: References: <20240605203723.643329-1-yang@os.amperecomputing.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240605203723.643329-1-yang@os.amperecomputing.com> On Wed, Jun 05, 2024 at 01:37:23PM -0700, Yang Shi wrote: > +static __always_inline bool aarch64_insn_is_class_cas(u32 insn) > +{ > + return aarch64_insn_is_cas(insn) || > + aarch64_insn_is_casp(insn); > +} > + > +/* > + * Exclude unallocated atomic instructions and LD64B/LDAPR. > + * The masks and values were generated by using Python sympy module. > + */ > +static __always_inline bool aarch64_atomic_insn_has_wr_perm(u32 insn) > +{ > + return ((insn & 0x3f207c00) == 0x38200000) || > + ((insn & 0x3f208c00) == 0x38200000) || > + ((insn & 0x7fe06c00) == 0x78202000) || > + ((insn & 0xbf204c00) == 0x38200000); > +} This is still pretty opaque if we want to modify it in the future. I guess we could add more tests on top but it would be nice to have a way to re-generate these masks. I'll think about, for now these tests would do. > @@ -511,6 +539,7 @@ static int __kprobes do_page_fault(unsigned long far, unsigned long esr, > unsigned long addr = untagged_addr(far); > struct vm_area_struct *vma; > int si_code; > + bool may_force_write = false; > > if (kprobe_page_fault(regs, esr)) > return 0; > @@ -547,6 +576,7 @@ static int __kprobes do_page_fault(unsigned long far, unsigned long esr, > /* If EPAN is absent then exec implies read */ > if (!alternative_has_cap_unlikely(ARM64_HAS_EPAN)) > vm_flags |= VM_EXEC; > + may_force_write = true; > } > > if (is_ttbr0_addr(addr) && is_el1_permission_fault(addr, esr, regs)) { > @@ -568,6 +598,12 @@ static int __kprobes do_page_fault(unsigned long far, unsigned long esr, > if (!vma) > goto lock_mmap; > > + if (may_force_write && (vma->vm_flags & VM_WRITE) && > + is_el0_atomic_instr(regs)) { > + vm_flags = VM_WRITE; > + mm_flags |= FAULT_FLAG_WRITE; > + } I think we can get rid of may_force_write and just test (vm_flags & VM_READ). -- Catalin