[PATCH V3 00/15] clk: imx: misc update/fix

[PATCH V3 00/15] clk: imx: misc update/fix

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

Changes in v3:
- Drop two patches
      clk: imx: pll14xx: Add constraint for fvco frequency
      clk: imx: pll14xx: use rate_table for audio plls
- Update 8ULP PCC check to not return Error
- Update commit log and Add R-b for 
  "clk: imx: imx8mp: fix clock tree update of TF-A managed clocks"
- Link to v2: https://lore.kernel.org/all/20240510-imx-clk-v2-0-c998f315d29c@nxp.com/


Changes in v2:
- Drop "clk: imx: pll14xx: potential integer overflow eliminated by
       casting to u64"
- Add Fixes tag  "clk: imx: imx8mp-audiomix: remove sdma root clock"
- Link to v1: https://lore.kernel.org/r/20240504-imx-clk-v1-0-f7915489d58d@nxp.com

Upstream several patches landed in NXP downstream repo for some time.
- i.MX8M/93/7ULP composite clk update
- Fix Fracn-gppll MFN got lost
- PLL14xx update
- i.MX8MP DRAM CLK fix
- i.MX8MM/N misc update
- Init i.MX8QXP parent clk before child clk

Downstream tags are kept for the patches got R-b

Although there are a few fixes, non-urgent for 6.10.

Adrian Alonso (1):
  clk: imx: imx8mn: add sai7_ipg_clk clock settings

Jacky Bai (2):
  clk: imx: composite-93: keep root clock on when mcore enabled
  clk: imx: imx8mm: Change the 'nand_usdhc_bus' clock to non-critical
    one

Oliver F. Brown (1):
  clk: imx: imx8qxp: Add clock muxes for MIPI and PHY ref clocks

Peng Fan (8):
  clk: imx: composite-8m: Enable gate clk with mcore_booted
  clk: imx: imx8mp-audiomix: remove sdma root clock
  clk: imx: Remove CLK_SET_PARENT_GATE for DRAM mux for i.MX7D
  clk: imx: add CLK_SET_RATE_PARENT for lcdif_pixel_src for i.MX7D
  clk: imx: imx8qxp: Add LVDS bypass clocks
  clk: imx: imx8qxp: Register dc0_bypass0_clk before disp clk
  clk: imx: imx8qxp: Parent should be initialized earlier than the clock
  clk: imx: fracn-gppll: update rate table

Pengfei Li (1):
  clk: imx: fracn-gppll: fix fractional part of PLL getting lost

Ye Li (1):
  clk: imx: composite-7ulp: Check the PCC present bit

Zhipeng Wang (1):
  clk: imx: imx8mp: fix clock tree update of TF-A managed clocks

 drivers/clk/imx/clk-composite-7ulp.c  |  7 ++++
 drivers/clk/imx/clk-composite-8m.c    | 53 +++++++++++++++++++++------
 drivers/clk/imx/clk-composite-93.c    | 15 ++++----
 drivers/clk/imx/clk-fracn-gppll.c     |  6 +++
 drivers/clk/imx/clk-imx7d.c           |  6 +--
 drivers/clk/imx/clk-imx8mm.c          |  2 +-
 drivers/clk/imx/clk-imx8mn.c          |  1 +
 drivers/clk/imx/clk-imx8mp-audiomix.c |  1 -
 drivers/clk/imx/clk-imx8mp.c          |  4 +-
 drivers/clk/imx/clk-imx8qxp.c         | 51 +++++++++++++++++---------
 10 files changed, 103 insertions(+), 43 deletions(-)

-- 
2.37.1

[PATCH V3 01/15] clk: imx: composite-8m: Enable gate clk with mcore_booted

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

Bootloader might disable some CCM ROOT Slices. So if mcore_booted set with
display CCM ROOT disabled by Bootloader, kernel display BLK CTRL driver
imx8m_blk_ctrl_driver_init may hang the system because the BUS clk is
disabled.

Add back gate ops, but with disable doing nothing, then the CCM ROOT
will be enabled when used.

Fixes: bb7e897b002a ("clk: imx8m: check mcore_booted before register clk")
Reviewed-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-composite-8m.c | 53 +++++++++++++++++++++++-------
 1 file changed, 42 insertions(+), 11 deletions(-)

diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c
index 8cc07d056a83..f187582ba491 100644
--- a/drivers/clk/imx/clk-composite-8m.c
+++ b/drivers/clk/imx/clk-composite-8m.c
@@ -204,6 +204,34 @@ static const struct clk_ops imx8m_clk_composite_mux_ops = {
 	.determine_rate = imx8m_clk_composite_mux_determine_rate,
 };
 
+static int imx8m_clk_composite_gate_enable(struct clk_hw *hw)
+{
+	struct clk_gate *gate = to_clk_gate(hw);
+	unsigned long flags;
+	u32 val;
+
+	spin_lock_irqsave(gate->lock, flags);
+
+	val = readl(gate->reg);
+	val |= BIT(gate->bit_idx);
+	writel(val, gate->reg);
+
+	spin_unlock_irqrestore(gate->lock, flags);
+
+	return 0;
+}
+
+static void imx8m_clk_composite_gate_disable(struct clk_hw *hw)
+{
+	/* composite clk requires the disable hook */
+}
+
+static const struct clk_ops imx8m_clk_composite_gate_ops = {
+	.enable = imx8m_clk_composite_gate_enable,
+	.disable = imx8m_clk_composite_gate_disable,
+	.is_enabled = clk_gate_is_enabled,
+};
+
 struct clk_hw *__imx8m_clk_hw_composite(const char *name,
 					const char * const *parent_names,
 					int num_parents, void __iomem *reg,
@@ -217,6 +245,7 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name,
 	struct clk_mux *mux;
 	const struct clk_ops *divider_ops;
 	const struct clk_ops *mux_ops;
+	const struct clk_ops *gate_ops;
 
 	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
 	if (!mux)
@@ -257,20 +286,22 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name,
 	div->flags = CLK_DIVIDER_ROUND_CLOSEST;
 
 	/* skip registering the gate ops if M4 is enabled */
-	if (!mcore_booted) {
-		gate = kzalloc(sizeof(*gate), GFP_KERNEL);
-		if (!gate)
-			goto free_div;
-
-		gate_hw = &gate->hw;
-		gate->reg = reg;
-		gate->bit_idx = PCG_CGC_SHIFT;
-		gate->lock = &imx_ccm_lock;
-	}
+	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+	if (!gate)
+		goto free_div;
+
+	gate_hw = &gate->hw;
+	gate->reg = reg;
+	gate->bit_idx = PCG_CGC_SHIFT;
+	gate->lock = &imx_ccm_lock;
+	if (!mcore_booted)
+		gate_ops = &clk_gate_ops;
+	else
+		gate_ops = &imx8m_clk_composite_gate_ops;
 
 	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
 			mux_hw, mux_ops, div_hw,
-			divider_ops, gate_hw, &clk_gate_ops, flags);
+			divider_ops, gate_hw, gate_ops, flags);
 	if (IS_ERR(hw))
 		goto free_gate;
 
-- 
2.37.1

[PATCH V3 02/15] clk: imx: composite-93: keep root clock on when mcore enabled

[Peng Fan (OSS)]

From: Jacky Bai <ping.bai@nxp.com>

Previously we assumed that the root clock slice is enabled
by default when kernel boot up. But the bootloader may disable
the clocks before jump into kernel. The gate ops should be registered
rather than NULL to make sure the disabled clock can be enabled
when kernel boot up.  Refine the code to skip disable the clock
if mcore booted.

Fixes: a740d7350ff7 ("clk: imx: imx93: add mcore_booted module paratemter")
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Chancel Liu <chancel.liu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-composite-93.c | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/imx/clk-composite-93.c b/drivers/clk/imx/clk-composite-93.c
index 81164bdcd6cc..6c6c5a30f328 100644
--- a/drivers/clk/imx/clk-composite-93.c
+++ b/drivers/clk/imx/clk-composite-93.c
@@ -76,6 +76,13 @@ static int imx93_clk_composite_gate_enable(struct clk_hw *hw)
 
 static void imx93_clk_composite_gate_disable(struct clk_hw *hw)
 {
+	/*
+	 * Skip disable the root clock gate if mcore enabled.
+	 * The root clock may be used by the mcore.
+	 */
+	if (mcore_booted)
+		return;
+
 	imx93_clk_composite_gate_endisable(hw, 0);
 }
 
@@ -222,7 +229,7 @@ struct clk_hw *imx93_clk_composite_flags(const char *name, const char * const *p
 		hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
 					       mux_hw, &clk_mux_ro_ops, div_hw,
 					       &clk_divider_ro_ops, NULL, NULL, flags);
-	} else if (!mcore_booted) {
+	} else {
 		gate = kzalloc(sizeof(*gate), GFP_KERNEL);
 		if (!gate)
 			goto fail;
@@ -238,12 +245,6 @@ struct clk_hw *imx93_clk_composite_flags(const char *name, const char * const *p
 					       &imx93_clk_composite_divider_ops, gate_hw,
 					       &imx93_clk_composite_gate_ops,
 					       flags | CLK_SET_RATE_NO_REPARENT);
-	} else {
-		hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
-					       mux_hw, &imx93_clk_composite_mux_ops, div_hw,
-					       &imx93_clk_composite_divider_ops, NULL,
-					       &imx93_clk_composite_gate_ops,
-					       flags | CLK_SET_RATE_NO_REPARENT);
 	}
 
 	if (IS_ERR(hw))
-- 
2.37.1

[PATCH V3 03/15] clk: imx: composite-7ulp: Check the PCC present bit

[Peng Fan (OSS)]

From: Ye Li <ye.li@nxp.com>

When some module is disabled by fuse, its PCC PR bit is default 0 and
PCC is not operational. Any write to this PCC will cause SError.

Fixes: b40ba8065347 ("clk: imx: Update the compsite driver to support imx8ulp")
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-composite-7ulp.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/clk/imx/clk-composite-7ulp.c b/drivers/clk/imx/clk-composite-7ulp.c
index e208ddc51133..db7f40b07d1a 100644
--- a/drivers/clk/imx/clk-composite-7ulp.c
+++ b/drivers/clk/imx/clk-composite-7ulp.c
@@ -14,6 +14,7 @@
 #include "../clk-fractional-divider.h"
 #include "clk.h"
 
+#define PCG_PR_MASK		BIT(31)
 #define PCG_PCS_SHIFT	24
 #define PCG_PCS_MASK	0x7
 #define PCG_CGC_SHIFT	30
@@ -78,6 +79,12 @@ static struct clk_hw *imx_ulp_clk_hw_composite(const char *name,
 	struct clk_hw *hw;
 	u32 val;
 
+	val = readl(reg);
+	if (!(val & PCG_PR_MASK)) {
+		pr_info("PCC PR is 0 for clk:%s, bypass\n", name);
+		return 0;
+	}
+
 	if (mux_present) {
 		mux = kzalloc(sizeof(*mux), GFP_KERNEL);
 		if (!mux)
-- 
2.37.1

[PATCH V3 04/15] clk: imx: fracn-gppll: fix fractional part of PLL getting lost

[Peng Fan (OSS)]

From: Pengfei Li <pengfei.li_1@nxp.com>

Fractional part of PLL gets lost after re-enabling the PLL. the
MFN can NOT be automatically loaded when doing frac PLL enable/disable,
So when re-enable PLL, configure mfn explicitly.

Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll")
Signed-off-by: Pengfei Li <pengfei.li_1@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-fracn-gppll.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c
index 44462ab50e51..1becba2b62d0 100644
--- a/drivers/clk/imx/clk-fracn-gppll.c
+++ b/drivers/clk/imx/clk-fracn-gppll.c
@@ -291,6 +291,10 @@ static int clk_fracn_gppll_prepare(struct clk_hw *hw)
 	if (val & POWERUP_MASK)
 		return 0;
 
+	if (pll->flags & CLK_FRACN_GPPLL_FRACN)
+		writel_relaxed(readl_relaxed(pll->base + PLL_NUMERATOR),
+			       pll->base + PLL_NUMERATOR);
+
 	val |= CLKMUX_BYPASS;
 	writel_relaxed(val, pll->base + PLL_CTRL);
 
-- 
2.37.1

[PATCH V3 05/15] clk: imx: imx8mp-audiomix: remove sdma root clock

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

There is an issue:
SDMA3 can't work without setting AUDIOMIX_CLKEN0[SDMA2] (bit-26) to 1

The workaround is:
As the reset state of AUDIOMIX_CLKEN0[SDMA2] is enabled,
we just need to keep it on as reset state, don't touch it
in kernel, then every thing is same as before, if we register
the clock in clk-audiomix, then kernel will try to disable
it in idle.

Fixes: 6cd95f7b151c ("clk: imx: imx8mp: Add audiomix block control")
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-imx8mp-audiomix.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/clk/imx/clk-imx8mp-audiomix.c b/drivers/clk/imx/clk-imx8mp-audiomix.c
index b381d6f784c8..88d8ba975b5a 100644
--- a/drivers/clk/imx/clk-imx8mp-audiomix.c
+++ b/drivers/clk/imx/clk-imx8mp-audiomix.c
@@ -172,7 +172,6 @@ static struct clk_imx8mp_audiomix_sel sels[] = {
 	CLK_GATE("ocrama", OCRAMA_IPG),
 	CLK_GATE("aud2htx", AUD2HTX_IPG),
 	CLK_GATE("earc_phy", EARC_PHY),
-	CLK_GATE("sdma2", SDMA2_ROOT),
 	CLK_GATE("sdma3", SDMA3_ROOT),
 	CLK_GATE("spba2", SPBA2_ROOT),
 	CLK_GATE("dsp", DSP_ROOT),
-- 
2.37.1

Re: [PATCH V3 05/15] clk: imx: imx8mp-audiomix: remove sdma root clock

[Adam Ford]

On Fri, Jun 7, 2024 at 8:28 AM Peng Fan (OSS) <peng.fan@oss.nxp.com> wrote:
>
> From: Peng Fan <peng.fan@nxp.com>
>
> There is an issue:
> SDMA3 can't work without setting AUDIOMIX_CLKEN0[SDMA2] (bit-26) to 1
>
> The workaround is:
> As the reset state of AUDIOMIX_CLKEN0[SDMA2] is enabled,
> we just need to keep it on as reset state, don't touch it
> in kernel, then every thing is same as before, if we register
> the clock in clk-audiomix, then kernel will try to disable
> it in idle.
>
> Fixes: 6cd95f7b151c ("clk: imx: imx8mp: Add audiomix block control")
> Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---

With this patch,I found it broke the imx8mp-beacon board when running
audio through a codec connected to sai3.  Reverting this patch made
the crash go away.  Is there a way to mark the clock as critical so it
doesn't get idled?

adam
>  drivers/clk/imx/clk-imx8mp-audiomix.c | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/drivers/clk/imx/clk-imx8mp-audiomix.c b/drivers/clk/imx/clk-imx8mp-audiomix.c
> index b381d6f784c8..88d8ba975b5a 100644
> --- a/drivers/clk/imx/clk-imx8mp-audiomix.c
> +++ b/drivers/clk/imx/clk-imx8mp-audiomix.c
> @@ -172,7 +172,6 @@ static struct clk_imx8mp_audiomix_sel sels[] = {
>         CLK_GATE("ocrama", OCRAMA_IPG),
>         CLK_GATE("aud2htx", AUD2HTX_IPG),
>         CLK_GATE("earc_phy", EARC_PHY),
> -       CLK_GATE("sdma2", SDMA2_ROOT),
>         CLK_GATE("sdma3", SDMA3_ROOT),
>         CLK_GATE("spba2", SPBA2_ROOT),
>         CLK_GATE("dsp", DSP_ROOT),
> --
> 2.37.1
>
>

RE: [PATCH V3 05/15] clk: imx: imx8mp-audiomix: remove sdma root clock

[Peng Fan]

> Subject: Re: [PATCH V3 05/15] clk: imx: imx8mp-audiomix: remove
> sdma root clock
> 
> On Fri, Jun 7, 2024 at 8:28 AM Peng Fan (OSS) <peng.fan@oss.nxp.com>
> wrote:
> >
> > From: Peng Fan <peng.fan@nxp.com>
> >
> > There is an issue:
> > SDMA3 can't work without setting AUDIOMIX_CLKEN0[SDMA2] (bit-
> 26) to 1
> >
> > The workaround is:
> > As the reset state of AUDIOMIX_CLKEN0[SDMA2] is enabled, we just
> need
> > to keep it on as reset state, don't touch it in kernel, then every
> > thing is same as before, if we register the clock in clk-audiomix,
> > then kernel will try to disable it in idle.
> >
> > Fixes: 6cd95f7b151c ("clk: imx: imx8mp: Add audiomix block
> control")
> > Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> 
> With this patch,I found it broke the imx8mp-beacon board when
> running audio through a codec connected to sai3.  Reverting this patch
> made the crash go away.  Is there a way to mark the clock as critical so
> it doesn't get idled?

Mark it as critical means the blk ctrl needs to be powered on always.

You driver touched the SDMA2_ROOT clock?

Regards,
Peng.

> 
> adam
> >  drivers/clk/imx/clk-imx8mp-audiomix.c | 1 -
> >  1 file changed, 1 deletion(-)
> >
> > diff --git a/drivers/clk/imx/clk-imx8mp-audiomix.c
> > b/drivers/clk/imx/clk-imx8mp-audiomix.c
> > index b381d6f784c8..88d8ba975b5a 100644
> > --- a/drivers/clk/imx/clk-imx8mp-audiomix.c
> > +++ b/drivers/clk/imx/clk-imx8mp-audiomix.c
> > @@ -172,7 +172,6 @@ static struct clk_imx8mp_audiomix_sel sels[]
> = {
> >         CLK_GATE("ocrama", OCRAMA_IPG),
> >         CLK_GATE("aud2htx", AUD2HTX_IPG),
> >         CLK_GATE("earc_phy", EARC_PHY),
> > -       CLK_GATE("sdma2", SDMA2_ROOT),
> >         CLK_GATE("sdma3", SDMA3_ROOT),
> >         CLK_GATE("spba2", SPBA2_ROOT),
> >         CLK_GATE("dsp", DSP_ROOT),
> > --
> > 2.37.1
> >
> >

Re: [PATCH V3 05/15] clk: imx: imx8mp-audiomix: remove sdma root clock

[Adam Ford]

On Sun, Jul 14, 2024 at 8:11 PM Peng Fan <peng.fan@nxp.com> wrote:
>
> > Subject: Re: [PATCH V3 05/15] clk: imx: imx8mp-audiomix: remove
> > sdma root clock
> >
> > On Fri, Jun 7, 2024 at 8:28 AM Peng Fan (OSS) <peng.fan@oss.nxp.com>
> > wrote:
> > >
> > > From: Peng Fan <peng.fan@nxp.com>
> > >
> > > There is an issue:
> > > SDMA3 can't work without setting AUDIOMIX_CLKEN0[SDMA2] (bit-
> > 26) to 1
> > >
> > > The workaround is:
> > > As the reset state of AUDIOMIX_CLKEN0[SDMA2] is enabled, we just
> > need
> > > to keep it on as reset state, don't touch it in kernel, then every
> > > thing is same as before, if we register the clock in clk-audiomix,
> > > then kernel will try to disable it in idle.
> > >
> > > Fixes: 6cd95f7b151c ("clk: imx: imx8mp: Add audiomix block
> > control")
> > > Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
> > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > ---
> >
> > With this patch,I found it broke the imx8mp-beacon board when
> > running audio through a codec connected to sai3.  Reverting this patch
> > made the crash go away.  Is there a way to mark the clock as critical so
> > it doesn't get idled?
>
> Mark it as critical means the blk ctrl needs to be powered on always.
>
> You driver touched the SDMA2_ROOT clock?

I have a WM8962 CODEC connected through sai3.  Without this patch, the
sound plays just fine.  With this patch, I get the following:

[   73.245199] imx-sdma 30e10000.dma-controller: Timeout waiting for CH0 ready
[   73.252197] ------------[ cut here ]------------
[   73.256816] WARNING: CPU: 1 PID: 1080 at kernel/dma/mapping.c:586
dma_free_attrs+0x94/0xc0
[   73.256832] Modules linked in: overlay af_alg dw_hdmi_gp_audio
dw_hdmi_cec tpm_tis_spi snd_soc_hdmi_codec caam_jr tpm_tis_core
caamhash_desc caamalg_desc crypto_engine authenc libdes hantro_vpu
v4l2_jpeg v4l2_vp9 v4l2_h264 v4l2_mem2mem videobuf2_dma_contig
videobuf2_memops videobuf2_v4l2 videodev imx8mp_hdmi_tx btnxpuart nvme
videobuf2_common dw_hdmi mc nvme_core etnaviv imx_lcdif bluetooth
fsl_imx8_ddr_perf drm_display_helper dwmac_imx gpu_sched
phy_fsl_samsung_hdmi imx8mp_hdmi_pvi drm_dma_helper samsung_dsim
snd_soc_fsl_sai stmmac_platform snd_soc_fsl_xcvr snd_soc_fsl_micfil
snd_soc_fsl_aud2htx stmmac adv7511 ecdh_generic imx_pcm_dma
snd_soc_fsl_utils ecc pcs_xpcs cec tcpci flexcan tcpm hd3ss3220
snd_soc_wm8962 spi_imx can_dev typec at24 caam rtc_pcf85363 rtc_snvs
error snvs_pwrkey imx8mm_thermal crct10dif_ce snd_soc_imx_hdmi
coresight_tmc snd_soc_imx_card snd_soc_simple_card coresight_funnel
snd_soc_simple_card_utils display_connector snd_soc_dmic coresight
drm_kms_helper imx_cpufreq_dt imx_sdma mwifiex_sdio
[   73.256997]  mwifiex cfg80211 rfkill fuse drm backlight ipv6
[   73.257015] CPU: 1 UID: 0 PID: 1080 Comm: speaker-test Not tainted
6.10.0-rc7-next-20240709-ga90ee5931efe-dirty #9
[   73.257022] Hardware name: Beacon EmbeddedWorks i.MX8MPlus
Development kit (DT)
[   73.257025] pstate: 600000c5 (nZCv daIF -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[   73.257031] pc : dma_free_attrs+0x94/0xc0
[   73.257037] lr : dma_free_attrs+0x50/0xc0
[   73.257041] sp : ffff800084f6b980
[   73.257043] x29: ffff800084f6b980 x28: 0000000000000010 x27: 00000000000003c2
[   73.257051] x26: 0000000000000005 x25: 0000000000000010 x24: 0000000000000000
[   73.257057] x23: 00000000c5504000 x22: 0000000000000000 x21: ffff800083183000
[   73.257064] x20: 00000000000000c0 x19: ffff0000c0e54410 x18: 0000000000000006
[   73.257071] x17: 0000000000000000 x16: 0000000000000000 x15: ffff800084f6b330
[   73.257078] x14: 0000000000000000 x13: ffff8000826845d8 x12: 0000000000000639
[   73.257085] x11: 0000000000000213 x10: ffff8000826dc5d8 x9 : ffff8000826845d8
[   73.257092] x8 : 00000000ffffefff x7 : ffff8000826dc5d8 x6 : 0000000000000040
[   73.257098] x5 : 0000000000000000 x4 : 0000000000000000 x3 : 00000000c5504000
[   73.257105] x2 : ffff800083183000 x1 : 0000000000000000 x0 : 00000000000000c0
[   73.257112] Call trace:
[   73.257115]  dma_free_attrs+0x94/0xc0
[   73.257121]  sdma_free_bd+0x60/0x6c [imx_sdma]
[   73.257130]  sdma_transfer_init+0x1e8/0x270 [imx_sdma]
[   73.257137]  sdma_prep_dma_cyclic+0x74/0x200 [imx_sdma]
[   73.257143]  snd_dmaengine_pcm_trigger+0xd8/0x18c
[   73.257152]  dmaengine_pcm_trigger+0x18/0x24
[   73.257159]  snd_soc_pcm_component_trigger+0x170/0x21c
[   73.257168]  soc_pcm_trigger+0xdc/0x1c8
[   73.257175]  snd_pcm_do_start+0x44/0x70
[   73.257183]  snd_pcm_action_single+0x48/0xa4
[   73.257189]  snd_pcm_action+0x80/0x9c
[   73.257195]  snd_pcm_start+0x24/0x30
[   73.257203]  __snd_pcm_lib_xfer+0x6a4/0x7d8
[   73.257208]  snd_pcm_common_ioctl+0x1140/0x1780
[   73.257215]  snd_pcm_ioctl+0x34/0x4c
[   73.257222]  __arm64_sys_ioctl+0xac/0xf0
[   73.257231]  invoke_syscall+0x48/0x114
[   73.257239]  el0_svc_common.constprop.0+0x40/0xe0
[   73.257246]  do_el0_svc+0x1c/0x28
[   73.257252]  el0_svc+0x34/0xd8
[   73.257260]  el0t_64_sync_handler+0x120/0x12c
[   73.257267]  el0t_64_sync+0x190/0x194
[   73.257273] ---[ end trace 0000000000000000 ]---
[   73.565659] fsl-sai 30c30000.sai: ASoC: error at
soc_component_trigger on 30c30000.sai: -12

Write error: -5,Input/output erro[   76.767120] imx-sdma
30e10000.dma-controller: Timeout waiting for CH0 ready

No sound is heard.

I haven't looked far into the driver to see what was touched, but I
was able to reproduce this by enabling and disabling the patch several
times, so it's repeatable. imx-sdma 30e10000.dma-controller seems to
correspond to sdma2.

adam
>
> Regards,
> Peng.
>
> >
> > adam
> > >  drivers/clk/imx/clk-imx8mp-audiomix.c | 1 -
> > >  1 file changed, 1 deletion(-)
> > >
> > > diff --git a/drivers/clk/imx/clk-imx8mp-audiomix.c
> > > b/drivers/clk/imx/clk-imx8mp-audiomix.c
> > > index b381d6f784c8..88d8ba975b5a 100644
> > > --- a/drivers/clk/imx/clk-imx8mp-audiomix.c
> > > +++ b/drivers/clk/imx/clk-imx8mp-audiomix.c
> > > @@ -172,7 +172,6 @@ static struct clk_imx8mp_audiomix_sel sels[]
> > = {
> > >         CLK_GATE("ocrama", OCRAMA_IPG),
> > >         CLK_GATE("aud2htx", AUD2HTX_IPG),
> > >         CLK_GATE("earc_phy", EARC_PHY),
> > > -       CLK_GATE("sdma2", SDMA2_ROOT),
> > >         CLK_GATE("sdma3", SDMA3_ROOT),
> > >         CLK_GATE("spba2", SPBA2_ROOT),
> > >         CLK_GATE("dsp", DSP_ROOT),
> > > --
> > > 2.37.1
> > >
> > >

RE: [PATCH V3 05/15] clk: imx: imx8mp-audiomix: remove sdma root clock

[Peng Fan]

> Subject: Re: [PATCH V3 05/15] clk: imx: imx8mp-audiomix: remove
> sdma root clock
> 
> On Sun, Jul 14, 2024 at 8:11 PM Peng Fan <peng.fan@nxp.com> wrote:
> >
> > > Subject: Re: [PATCH V3 05/15] clk: imx: imx8mp-audiomix: remove
> sdma
> > > root clock
> > >
> > > On Fri, Jun 7, 2024 at 8:28 AM Peng Fan (OSS)
> <peng.fan@oss.nxp.com>
> > > wrote:
> > > >
> > > > From: Peng Fan <peng.fan@nxp.com>
> > > >
> > > > There is an issue:
> > > > SDMA3 can't work without setting AUDIOMIX_CLKEN0[SDMA2]
> (bit-
> > > 26) to 1
> > > >
> > > > The workaround is:
> > > > As the reset state of AUDIOMIX_CLKEN0[SDMA2] is enabled, we
> just
> > > need
> > > > to keep it on as reset state, don't touch it in kernel, then every
> > > > thing is same as before, if we register the clock in clk-audiomix,
> > > > then kernel will try to disable it in idle.
> > > >
> > > > Fixes: 6cd95f7b151c ("clk: imx: imx8mp: Add audiomix block
> > > control")
> > > > Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
> > > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > > ---
> > >
> > > With this patch,I found it broke the imx8mp-beacon board when
> > > running audio through a codec connected to sai3.  Reverting this
> > > patch made the crash go away.  Is there a way to mark the clock as
> > > critical so it doesn't get idled?
> >
> > Mark it as critical means the blk ctrl needs to be powered on always.
> >
> > You driver touched the SDMA2_ROOT clock?
> 
> I have a WM8962 CODEC connected through sai3.  Without this patch,
> the sound plays just fine.  With this patch, I get the following:

Try use this for SDMA2.
                                clocks = <&clk IMX8MP_CLK_AUDIO_AHB_ROOT>,                          
                                         <&clk IMX8MP_CLK_AUDIO_AHB_ROOT>;

I will give a look and see how to address the issue.

Thanks for the report.

Thanks,
Peng.

> 
> [   73.245199] imx-sdma 30e10000.dma-controller: Timeout waiting
> for CH0 ready
> [   73.252197] ------------[ cut here ]------------
> [   73.256816] WARNING: CPU: 1 PID: 1080 at
> kernel/dma/mapping.c:586
> dma_free_attrs+0x94/0xc0
> [   73.256832] Modules linked in: overlay af_alg dw_hdmi_gp_audio
> dw_hdmi_cec tpm_tis_spi snd_soc_hdmi_codec caam_jr tpm_tis_core
> caamhash_desc caamalg_desc crypto_engine authenc libdes
> hantro_vpu v4l2_jpeg v4l2_vp9 v4l2_h264 v4l2_mem2mem
> videobuf2_dma_contig videobuf2_memops videobuf2_v4l2 videodev
> imx8mp_hdmi_tx btnxpuart nvme videobuf2_common dw_hdmi mc
> nvme_core etnaviv imx_lcdif bluetooth fsl_imx8_ddr_perf
> drm_display_helper dwmac_imx gpu_sched phy_fsl_samsung_hdmi
> imx8mp_hdmi_pvi drm_dma_helper samsung_dsim snd_soc_fsl_sai
> stmmac_platform snd_soc_fsl_xcvr snd_soc_fsl_micfil
> snd_soc_fsl_aud2htx stmmac adv7511 ecdh_generic imx_pcm_dma
> snd_soc_fsl_utils ecc pcs_xpcs cec tcpci flexcan tcpm hd3ss3220
> snd_soc_wm8962 spi_imx can_dev typec at24 caam rtc_pcf85363
> rtc_snvs error snvs_pwrkey imx8mm_thermal crct10dif_ce
> snd_soc_imx_hdmi coresight_tmc snd_soc_imx_card
> snd_soc_simple_card coresight_funnel snd_soc_simple_card_utils
> display_connector snd_soc_dmic coresight drm_kms_helper
> imx_cpufreq_dt imx_sdma mwifiex_sdio
> [   73.256997]  mwifiex cfg80211 rfkill fuse drm backlight ipv6
> [   73.257015] CPU: 1 UID: 0 PID: 1080 Comm: speaker-test Not
> tainted
> 6.10.0-rc7-next-20240709-ga90ee5931efe-dirty #9
> [   73.257022] Hardware name: Beacon EmbeddedWorks i.MX8MPlus
> Development kit (DT)
> [   73.257025] pstate: 600000c5 (nZCv daIF -PAN -UAO -TCO -DIT -SSBS
> BTYPE=--)
> [   73.257031] pc : dma_free_attrs+0x94/0xc0
> [   73.257037] lr : dma_free_attrs+0x50/0xc0
> [   73.257041] sp : ffff800084f6b980
> [   73.257043] x29: ffff800084f6b980 x28: 0000000000000010 x27:
> 00000000000003c2
> [   73.257051] x26: 0000000000000005 x25: 0000000000000010 x24:
> 0000000000000000
> [   73.257057] x23: 00000000c5504000 x22: 0000000000000000 x21:
> ffff800083183000
> [   73.257064] x20: 00000000000000c0 x19: ffff0000c0e54410 x18:
> 0000000000000006
> [   73.257071] x17: 0000000000000000 x16: 0000000000000000 x15:
> ffff800084f6b330
> [   73.257078] x14: 0000000000000000 x13: ffff8000826845d8 x12:
> 0000000000000639
> [   73.257085] x11: 0000000000000213 x10: ffff8000826dc5d8 x9 :
> ffff8000826845d8
> [   73.257092] x8 : 00000000ffffefff x7 : ffff8000826dc5d8 x6 :
> 0000000000000040
> [   73.257098] x5 : 0000000000000000 x4 : 0000000000000000 x3 :
> 00000000c5504000
> [   73.257105] x2 : ffff800083183000 x1 : 0000000000000000 x0 :
> 00000000000000c0
> [   73.257112] Call trace:
> [   73.257115]  dma_free_attrs+0x94/0xc0
> [   73.257121]  sdma_free_bd+0x60/0x6c [imx_sdma]
> [   73.257130]  sdma_transfer_init+0x1e8/0x270 [imx_sdma]
> [   73.257137]  sdma_prep_dma_cyclic+0x74/0x200 [imx_sdma]
> [   73.257143]  snd_dmaengine_pcm_trigger+0xd8/0x18c
> [   73.257152]  dmaengine_pcm_trigger+0x18/0x24
> [   73.257159]  snd_soc_pcm_component_trigger+0x170/0x21c
> [   73.257168]  soc_pcm_trigger+0xdc/0x1c8
> [   73.257175]  snd_pcm_do_start+0x44/0x70
> [   73.257183]  snd_pcm_action_single+0x48/0xa4
> [   73.257189]  snd_pcm_action+0x80/0x9c
> [   73.257195]  snd_pcm_start+0x24/0x30
> [   73.257203]  __snd_pcm_lib_xfer+0x6a4/0x7d8
> [   73.257208]  snd_pcm_common_ioctl+0x1140/0x1780
> [   73.257215]  snd_pcm_ioctl+0x34/0x4c
> [   73.257222]  __arm64_sys_ioctl+0xac/0xf0
> [   73.257231]  invoke_syscall+0x48/0x114
> [   73.257239]  el0_svc_common.constprop.0+0x40/0xe0
> [   73.257246]  do_el0_svc+0x1c/0x28
> [   73.257252]  el0_svc+0x34/0xd8
> [   73.257260]  el0t_64_sync_handler+0x120/0x12c
> [   73.257267]  el0t_64_sync+0x190/0x194
> [   73.257273] ---[ end trace 0000000000000000 ]---
> [   73.565659] fsl-sai 30c30000.sai: ASoC: error at
> soc_component_trigger on 30c30000.sai: -12
> 
> Write error: -5,Input/output erro[   76.767120] imx-sdma
> 30e10000.dma-controller: Timeout waiting for CH0 ready
> 
> No sound is heard.
> 
> I haven't looked far into the driver to see what was touched, but I was
> able to reproduce this by enabling and disabling the patch several
> times, so it's repeatable. imx-sdma 30e10000.dma-controller seems to
> correspond to sdma2.
> 
> adam
> >
> > Regards,
> > Peng.
> >
> > >
> > > adam
> > > >  drivers/clk/imx/clk-imx8mp-audiomix.c | 1 -
> > > >  1 file changed, 1 deletion(-)
> > > >
> > > > diff --git a/drivers/clk/imx/clk-imx8mp-audiomix.c
> > > > b/drivers/clk/imx/clk-imx8mp-audiomix.c
> > > > index b381d6f784c8..88d8ba975b5a 100644
> > > > --- a/drivers/clk/imx/clk-imx8mp-audiomix.c
> > > > +++ b/drivers/clk/imx/clk-imx8mp-audiomix.c
> > > > @@ -172,7 +172,6 @@ static struct clk_imx8mp_audiomix_sel
> sels[]
> > > = {
> > > >         CLK_GATE("ocrama", OCRAMA_IPG),
> > > >         CLK_GATE("aud2htx", AUD2HTX_IPG),
> > > >         CLK_GATE("earc_phy", EARC_PHY),
> > > > -       CLK_GATE("sdma2", SDMA2_ROOT),
> > > >         CLK_GATE("sdma3", SDMA3_ROOT),
> > > >         CLK_GATE("spba2", SPBA2_ROOT),
> > > >         CLK_GATE("dsp", DSP_ROOT),
> > > > --
> > > > 2.37.1
> > > >
> > > >

Re: [PATCH V3 05/15] clk: imx: imx8mp-audiomix: remove sdma root clock

[Adam Ford]

On Mon, Jul 15, 2024 at 8:25 PM Peng Fan <peng.fan@nxp.com> wrote:
>
> > Subject: Re: [PATCH V3 05/15] clk: imx: imx8mp-audiomix: remove
> > sdma root clock
> >
> > On Sun, Jul 14, 2024 at 8:11 PM Peng Fan <peng.fan@nxp.com> wrote:
> > >
> > > > Subject: Re: [PATCH V3 05/15] clk: imx: imx8mp-audiomix: remove
> > sdma
> > > > root clock
> > > >
> > > > On Fri, Jun 7, 2024 at 8:28 AM Peng Fan (OSS)
> > <peng.fan@oss.nxp.com>
> > > > wrote:
> > > > >
> > > > > From: Peng Fan <peng.fan@nxp.com>
> > > > >
> > > > > There is an issue:
> > > > > SDMA3 can't work without setting AUDIOMIX_CLKEN0[SDMA2]
> > (bit-
> > > > 26) to 1
> > > > >
> > > > > The workaround is:
> > > > > As the reset state of AUDIOMIX_CLKEN0[SDMA2] is enabled, we
> > just
> > > > need
> > > > > to keep it on as reset state, don't touch it in kernel, then every
> > > > > thing is same as before, if we register the clock in clk-audiomix,
> > > > > then kernel will try to disable it in idle.
> > > > >
> > > > > Fixes: 6cd95f7b151c ("clk: imx: imx8mp: Add audiomix block
> > > > control")
> > > > > Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
> > > > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > > > ---
> > > >
> > > > With this patch,I found it broke the imx8mp-beacon board when
> > > > running audio through a codec connected to sai3.  Reverting this
> > > > patch made the crash go away.  Is there a way to mark the clock as
> > > > critical so it doesn't get idled?
> > >
> > > Mark it as critical means the blk ctrl needs to be powered on always.
> > >
> > > You driver touched the SDMA2_ROOT clock?
> >
> > I have a WM8962 CODEC connected through sai3.  Without this patch,
> > the sound plays just fine.  With this patch, I get the following:
>
> Try use this for SDMA2.
>                                 clocks = <&clk IMX8MP_CLK_AUDIO_AHB_ROOT>,
>                                          <&clk IMX8MP_CLK_AUDIO_AHB_ROOT>;
>

Unfortunately, that didn't work either.  Changing the SDMA2 clocks to
the above yields the following:

[   20.714987] fsl-micfil-dai 30ca0000.audio-controller: failed to pcm register
[   20.728904] fsl-aud2htx 30cb0000.aud2htx: failed to pcm register
[   20.755070] fsl,imx8mp-audio-xcvr 30cc0000.xcvr: failed to pcm register
[   20.766373] platform 30c50000.sai: deferred probe pending: fsl-sai:
PCM DMA init failed
[   20.774497] platform 30ca0000.audio-controller: deferred probe
pending: (reason unknown)
[   20.786387] platform 30cb0000.aud2htx: deferred probe pending:
(reason unknown)
[   20.793761] platform sound-dmic: deferred probe pending:
asoc-simple-card: parse error
[   20.806374] platform sound-wm8962: deferred probe pending:
asoc-simple-card: parse error
[   20.814526] platform sound-hdmi: deferred probe pending: imx-hdmi:
snd_soc_register_card failed
[   20.826370] platform 30c30000.sai: deferred probe pending: fsl-sai:
PCM DMA init failed
[   20.834429] platform sound-xcvr: deferred probe pending: imx-card:
XCVR PCM: error getting cpu dai info
[   20.846402] platform 30cc0000.xcvr: deferred probe pending: (reason unknown)
[   20.858378] platform sound-adv7535: deferred probe pending:
asoc-simple-card: parse error


adam

> I will give a look and see how to address the issue.
>
> Thanks for the report.
>
> Thanks,
> Peng.
>
> >
> > [   73.245199] imx-sdma 30e10000.dma-controller: Timeout waiting
> > for CH0 ready
> > [   73.252197] ------------[ cut here ]------------
> > [   73.256816] WARNING: CPU: 1 PID: 1080 at
> > kernel/dma/mapping.c:586
> > dma_free_attrs+0x94/0xc0
> > [   73.256832] Modules linked in: overlay af_alg dw_hdmi_gp_audio
> > dw_hdmi_cec tpm_tis_spi snd_soc_hdmi_codec caam_jr tpm_tis_core
> > caamhash_desc caamalg_desc crypto_engine authenc libdes
> > hantro_vpu v4l2_jpeg v4l2_vp9 v4l2_h264 v4l2_mem2mem
> > videobuf2_dma_contig videobuf2_memops videobuf2_v4l2 videodev
> > imx8mp_hdmi_tx btnxpuart nvme videobuf2_common dw_hdmi mc
> > nvme_core etnaviv imx_lcdif bluetooth fsl_imx8_ddr_perf
> > drm_display_helper dwmac_imx gpu_sched phy_fsl_samsung_hdmi
> > imx8mp_hdmi_pvi drm_dma_helper samsung_dsim snd_soc_fsl_sai
> > stmmac_platform snd_soc_fsl_xcvr snd_soc_fsl_micfil
> > snd_soc_fsl_aud2htx stmmac adv7511 ecdh_generic imx_pcm_dma
> > snd_soc_fsl_utils ecc pcs_xpcs cec tcpci flexcan tcpm hd3ss3220
> > snd_soc_wm8962 spi_imx can_dev typec at24 caam rtc_pcf85363
> > rtc_snvs error snvs_pwrkey imx8mm_thermal crct10dif_ce
> > snd_soc_imx_hdmi coresight_tmc snd_soc_imx_card
> > snd_soc_simple_card coresight_funnel snd_soc_simple_card_utils
> > display_connector snd_soc_dmic coresight drm_kms_helper
> > imx_cpufreq_dt imx_sdma mwifiex_sdio
> > [   73.256997]  mwifiex cfg80211 rfkill fuse drm backlight ipv6
> > [   73.257015] CPU: 1 UID: 0 PID: 1080 Comm: speaker-test Not
> > tainted
> > 6.10.0-rc7-next-20240709-ga90ee5931efe-dirty #9
> > [   73.257022] Hardware name: Beacon EmbeddedWorks i.MX8MPlus
> > Development kit (DT)
> > [   73.257025] pstate: 600000c5 (nZCv daIF -PAN -UAO -TCO -DIT -SSBS
> > BTYPE=--)
> > [   73.257031] pc : dma_free_attrs+0x94/0xc0
> > [   73.257037] lr : dma_free_attrs+0x50/0xc0
> > [   73.257041] sp : ffff800084f6b980
> > [   73.257043] x29: ffff800084f6b980 x28: 0000000000000010 x27:
> > 00000000000003c2
> > [   73.257051] x26: 0000000000000005 x25: 0000000000000010 x24:
> > 0000000000000000
> > [   73.257057] x23: 00000000c5504000 x22: 0000000000000000 x21:
> > ffff800083183000
> > [   73.257064] x20: 00000000000000c0 x19: ffff0000c0e54410 x18:
> > 0000000000000006
> > [   73.257071] x17: 0000000000000000 x16: 0000000000000000 x15:
> > ffff800084f6b330
> > [   73.257078] x14: 0000000000000000 x13: ffff8000826845d8 x12:
> > 0000000000000639
> > [   73.257085] x11: 0000000000000213 x10: ffff8000826dc5d8 x9 :
> > ffff8000826845d8
> > [   73.257092] x8 : 00000000ffffefff x7 : ffff8000826dc5d8 x6 :
> > 0000000000000040
> > [   73.257098] x5 : 0000000000000000 x4 : 0000000000000000 x3 :
> > 00000000c5504000
> > [   73.257105] x2 : ffff800083183000 x1 : 0000000000000000 x0 :
> > 00000000000000c0
> > [   73.257112] Call trace:
> > [   73.257115]  dma_free_attrs+0x94/0xc0
> > [   73.257121]  sdma_free_bd+0x60/0x6c [imx_sdma]
> > [   73.257130]  sdma_transfer_init+0x1e8/0x270 [imx_sdma]
> > [   73.257137]  sdma_prep_dma_cyclic+0x74/0x200 [imx_sdma]
> > [   73.257143]  snd_dmaengine_pcm_trigger+0xd8/0x18c
> > [   73.257152]  dmaengine_pcm_trigger+0x18/0x24
> > [   73.257159]  snd_soc_pcm_component_trigger+0x170/0x21c
> > [   73.257168]  soc_pcm_trigger+0xdc/0x1c8
> > [   73.257175]  snd_pcm_do_start+0x44/0x70
> > [   73.257183]  snd_pcm_action_single+0x48/0xa4
> > [   73.257189]  snd_pcm_action+0x80/0x9c
> > [   73.257195]  snd_pcm_start+0x24/0x30
> > [   73.257203]  __snd_pcm_lib_xfer+0x6a4/0x7d8
> > [   73.257208]  snd_pcm_common_ioctl+0x1140/0x1780
> > [   73.257215]  snd_pcm_ioctl+0x34/0x4c
> > [   73.257222]  __arm64_sys_ioctl+0xac/0xf0
> > [   73.257231]  invoke_syscall+0x48/0x114
> > [   73.257239]  el0_svc_common.constprop.0+0x40/0xe0
> > [   73.257246]  do_el0_svc+0x1c/0x28
> > [   73.257252]  el0_svc+0x34/0xd8
> > [   73.257260]  el0t_64_sync_handler+0x120/0x12c
> > [   73.257267]  el0t_64_sync+0x190/0x194
> > [   73.257273] ---[ end trace 0000000000000000 ]---
> > [   73.565659] fsl-sai 30c30000.sai: ASoC: error at
> > soc_component_trigger on 30c30000.sai: -12
> >
> > Write error: -5,Input/output erro[   76.767120] imx-sdma
> > 30e10000.dma-controller: Timeout waiting for CH0 ready
> >
> > No sound is heard.
> >
> > I haven't looked far into the driver to see what was touched, but I was
> > able to reproduce this by enabling and disabling the patch several
> > times, so it's repeatable. imx-sdma 30e10000.dma-controller seems to
> > correspond to sdma2.
> >
> > adam
> > >
> > > Regards,
> > > Peng.
> > >
> > > >
> > > > adam
> > > > >  drivers/clk/imx/clk-imx8mp-audiomix.c | 1 -
> > > > >  1 file changed, 1 deletion(-)
> > > > >
> > > > > diff --git a/drivers/clk/imx/clk-imx8mp-audiomix.c
> > > > > b/drivers/clk/imx/clk-imx8mp-audiomix.c
> > > > > index b381d6f784c8..88d8ba975b5a 100644
> > > > > --- a/drivers/clk/imx/clk-imx8mp-audiomix.c
> > > > > +++ b/drivers/clk/imx/clk-imx8mp-audiomix.c
> > > > > @@ -172,7 +172,6 @@ static struct clk_imx8mp_audiomix_sel
> > sels[]
> > > > = {
> > > > >         CLK_GATE("ocrama", OCRAMA_IPG),
> > > > >         CLK_GATE("aud2htx", AUD2HTX_IPG),
> > > > >         CLK_GATE("earc_phy", EARC_PHY),
> > > > > -       CLK_GATE("sdma2", SDMA2_ROOT),
> > > > >         CLK_GATE("sdma3", SDMA3_ROOT),
> > > > >         CLK_GATE("spba2", SPBA2_ROOT),
> > > > >         CLK_GATE("dsp", DSP_ROOT),
> > > > > --
> > > > > 2.37.1
> > > > >
> > > > >

RE: [PATCH V3 05/15] clk: imx: imx8mp-audiomix: remove sdma root clock

[Peng Fan]

> Subject: Re: [PATCH V3 05/15] clk: imx: imx8mp-audiomix: remove
> sdma root clock
> 
> On Mon, Jul 15, 2024 at 8:25 PM Peng Fan <peng.fan@nxp.com>
> wrote:
> >
> > > Subject: Re: [PATCH V3 05/15] clk: imx: imx8mp-audiomix: remove
> sdma
> > > root clock
> > >
> > > On Sun, Jul 14, 2024 at 8:11 PM Peng Fan <peng.fan@nxp.com>
> wrote:
> > > >
> > > > > Subject: Re: [PATCH V3 05/15] clk: imx: imx8mp-audiomix:
> remove
> > > sdma
> > > > > root clock
> > > > >
> > > > > On Fri, Jun 7, 2024 at 8:28 AM Peng Fan (OSS)
> > > <peng.fan@oss.nxp.com>
> > > > > wrote:
> > > > > >
> > > > > > From: Peng Fan <peng.fan@nxp.com>
> > > > > >
> > > > > > There is an issue:
> > > > > > SDMA3 can't work without setting
> AUDIOMIX_CLKEN0[SDMA2]
> > > (bit-
> > > > > 26) to 1
> > > > > >
> > > > > > The workaround is:
> > > > > > As the reset state of AUDIOMIX_CLKEN0[SDMA2] is enabled,
> we
> > > just
> > > > > need
> > > > > > to keep it on as reset state, don't touch it in kernel, then
> > > > > > every thing is same as before, if we register the clock in
> > > > > > clk-audiomix, then kernel will try to disable it in idle.
> > > > > >
> > > > > > Fixes: 6cd95f7b151c ("clk: imx: imx8mp: Add audiomix block
> > > > > control")
> > > > > > Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
> > > > > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > > > > ---
> > > > >
> > > > > With this patch,I found it broke the imx8mp-beacon board
> when
> > > > > running audio through a codec connected to sai3.  Reverting
> this
> > > > > patch made the crash go away.  Is there a way to mark the clock
> > > > > as critical so it doesn't get idled?
> > > >
> > > > Mark it as critical means the blk ctrl needs to be powered on
> always.
> > > >
> > > > You driver touched the SDMA2_ROOT clock?
> > >
> > > I have a WM8962 CODEC connected through sai3.  Without this
> patch,
> > > the sound plays just fine.  With this patch, I get the following:
> >
> > Try use this for SDMA2.
> >                                 clocks = <&clk IMX8MP_CLK_AUDIO_AHB_ROOT>,
> >                                          <&clk
> > IMX8MP_CLK_AUDIO_AHB_ROOT>;
> >
> 
> Unfortunately, that didn't work either.  Changing the SDMA2 clocks to
> the above yields the following:

Shengjiu,

Do you have any ideas?

Thanks,
Peng.

> 
> [   20.714987] fsl-micfil-dai 30ca0000.audio-controller: failed to pcm
> register
> [   20.728904] fsl-aud2htx 30cb0000.aud2htx: failed to pcm register
> [   20.755070] fsl,imx8mp-audio-xcvr 30cc0000.xcvr: failed to pcm
> register
> [   20.766373] platform 30c50000.sai: deferred probe pending: fsl-sai:
> PCM DMA init failed
> [   20.774497] platform 30ca0000.audio-controller: deferred probe
> pending: (reason unknown)
> [   20.786387] platform 30cb0000.aud2htx: deferred probe pending:
> (reason unknown)
> [   20.793761] platform sound-dmic: deferred probe pending:
> asoc-simple-card: parse error
> [   20.806374] platform sound-wm8962: deferred probe pending:
> asoc-simple-card: parse error
> [   20.814526] platform sound-hdmi: deferred probe pending: imx-
> hdmi:
> snd_soc_register_card failed
> [   20.826370] platform 30c30000.sai: deferred probe pending: fsl-sai:
> PCM DMA init failed
> [   20.834429] platform sound-xcvr: deferred probe pending: imx-card:
> XCVR PCM: error getting cpu dai info
> [   20.846402] platform 30cc0000.xcvr: deferred probe pending:
> (reason unknown)
> [   20.858378] platform sound-adv7535: deferred probe pending:
> asoc-simple-card: parse error
> 
> 
> adam
> 
> > I will give a look and see how to address the issue.
> >
> > Thanks for the report.
> >
> > Thanks,
> > Peng.
> >
> > >
> > > [   73.245199] imx-sdma 30e10000.dma-controller: Timeout
> waiting
> > > for CH0 ready
> > > [   73.252197] ------------[ cut here ]------------
> > > [   73.256816] WARNING: CPU: 1 PID: 1080 at
> > > kernel/dma/mapping.c:586
> > > dma_free_attrs+0x94/0xc0
> > > [   73.256832] Modules linked in: overlay af_alg
> dw_hdmi_gp_audio
> > > dw_hdmi_cec tpm_tis_spi snd_soc_hdmi_codec caam_jr
> tpm_tis_core
> > > caamhash_desc caamalg_desc crypto_engine authenc libdes
> hantro_vpu
> > > v4l2_jpeg v4l2_vp9 v4l2_h264 v4l2_mem2mem
> videobuf2_dma_contig
> > > videobuf2_memops videobuf2_v4l2 videodev imx8mp_hdmi_tx
> btnxpuart
> > > nvme videobuf2_common dw_hdmi mc nvme_core etnaviv
> imx_lcdif
> > > bluetooth fsl_imx8_ddr_perf drm_display_helper dwmac_imx
> gpu_sched
> > > phy_fsl_samsung_hdmi imx8mp_hdmi_pvi drm_dma_helper
> samsung_dsim
> > > snd_soc_fsl_sai stmmac_platform snd_soc_fsl_xcvr
> snd_soc_fsl_micfil
> > > snd_soc_fsl_aud2htx stmmac adv7511 ecdh_generic imx_pcm_dma
> > > snd_soc_fsl_utils ecc pcs_xpcs cec tcpci flexcan tcpm hd3ss3220
> > > snd_soc_wm8962 spi_imx can_dev typec at24 caam rtc_pcf85363
> rtc_snvs
> > > error snvs_pwrkey imx8mm_thermal crct10dif_ce
> snd_soc_imx_hdmi
> > > coresight_tmc snd_soc_imx_card snd_soc_simple_card
> coresight_funnel
> > > snd_soc_simple_card_utils display_connector snd_soc_dmic
> coresight
> > > drm_kms_helper imx_cpufreq_dt imx_sdma mwifiex_sdio
> > > [   73.256997]  mwifiex cfg80211 rfkill fuse drm backlight ipv6
> > > [   73.257015] CPU: 1 UID: 0 PID: 1080 Comm: speaker-test Not
> > > tainted
> > > 6.10.0-rc7-next-20240709-ga90ee5931efe-dirty #9
> > > [   73.257022] Hardware name: Beacon EmbeddedWorks
> i.MX8MPlus
> > > Development kit (DT)
> > > [   73.257025] pstate: 600000c5 (nZCv daIF -PAN -UAO -TCO -DIT -
> SSBS
> > > BTYPE=--)
> > > [   73.257031] pc : dma_free_attrs+0x94/0xc0
> > > [   73.257037] lr : dma_free_attrs+0x50/0xc0
> > > [   73.257041] sp : ffff800084f6b980
> > > [   73.257043] x29: ffff800084f6b980 x28: 0000000000000010 x27:
> > > 00000000000003c2
> > > [   73.257051] x26: 0000000000000005 x25: 0000000000000010
> x24:
> > > 0000000000000000
> > > [   73.257057] x23: 00000000c5504000 x22: 0000000000000000
> x21:
> > > ffff800083183000
> > > [   73.257064] x20: 00000000000000c0 x19: ffff0000c0e54410 x18:
> > > 0000000000000006
> > > [   73.257071] x17: 0000000000000000 x16: 0000000000000000
> x15:
> > > ffff800084f6b330
> > > [   73.257078] x14: 0000000000000000 x13: ffff8000826845d8
> x12:
> > > 0000000000000639
> > > [   73.257085] x11: 0000000000000213 x10: ffff8000826dc5d8 x9 :
> > > ffff8000826845d8
> > > [   73.257092] x8 : 00000000ffffefff x7 : ffff8000826dc5d8 x6 :
> > > 0000000000000040
> > > [   73.257098] x5 : 0000000000000000 x4 : 0000000000000000
> x3 :
> > > 00000000c5504000
> > > [   73.257105] x2 : ffff800083183000 x1 : 0000000000000000 x0 :
> > > 00000000000000c0
> > > [   73.257112] Call trace:
> > > [   73.257115]  dma_free_attrs+0x94/0xc0
> > > [   73.257121]  sdma_free_bd+0x60/0x6c [imx_sdma]
> > > [   73.257130]  sdma_transfer_init+0x1e8/0x270 [imx_sdma]
> > > [   73.257137]  sdma_prep_dma_cyclic+0x74/0x200 [imx_sdma]
> > > [   73.257143]  snd_dmaengine_pcm_trigger+0xd8/0x18c
> > > [   73.257152]  dmaengine_pcm_trigger+0x18/0x24
> > > [   73.257159]  snd_soc_pcm_component_trigger+0x170/0x21c
> > > [   73.257168]  soc_pcm_trigger+0xdc/0x1c8
> > > [   73.257175]  snd_pcm_do_start+0x44/0x70
> > > [   73.257183]  snd_pcm_action_single+0x48/0xa4
> > > [   73.257189]  snd_pcm_action+0x80/0x9c
> > > [   73.257195]  snd_pcm_start+0x24/0x30
> > > [   73.257203]  __snd_pcm_lib_xfer+0x6a4/0x7d8
> > > [   73.257208]  snd_pcm_common_ioctl+0x1140/0x1780
> > > [   73.257215]  snd_pcm_ioctl+0x34/0x4c
> > > [   73.257222]  __arm64_sys_ioctl+0xac/0xf0
> > > [   73.257231]  invoke_syscall+0x48/0x114
> > > [   73.257239]  el0_svc_common.constprop.0+0x40/0xe0
> > > [   73.257246]  do_el0_svc+0x1c/0x28
> > > [   73.257252]  el0_svc+0x34/0xd8
> > > [   73.257260]  el0t_64_sync_handler+0x120/0x12c
> > > [   73.257267]  el0t_64_sync+0x190/0x194
> > > [   73.257273] ---[ end trace 0000000000000000 ]---
> > > [   73.565659] fsl-sai 30c30000.sai: ASoC: error at
> > > soc_component_trigger on 30c30000.sai: -12
> > >
> > > Write error: -5,Input/output erro[   76.767120] imx-sdma
> > > 30e10000.dma-controller: Timeout waiting for CH0 ready
> > >
> > > No sound is heard.
> > >
> > > I haven't looked far into the driver to see what was touched, but I
> > > was able to reproduce this by enabling and disabling the patch
> > > several times, so it's repeatable. imx-sdma 30e10000.dma-
> controller
> > > seems to correspond to sdma2.
> > >
> > > adam
> > > >
> > > > Regards,
> > > > Peng.
> > > >
> > > > >
> > > > > adam
> > > > > >  drivers/clk/imx/clk-imx8mp-audiomix.c | 1 -
> > > > > >  1 file changed, 1 deletion(-)
> > > > > >
> > > > > > diff --git a/drivers/clk/imx/clk-imx8mp-audiomix.c
> > > > > > b/drivers/clk/imx/clk-imx8mp-audiomix.c
> > > > > > index b381d6f784c8..88d8ba975b5a 100644
> > > > > > --- a/drivers/clk/imx/clk-imx8mp-audiomix.c
> > > > > > +++ b/drivers/clk/imx/clk-imx8mp-audiomix.c
> > > > > > @@ -172,7 +172,6 @@ static struct
> clk_imx8mp_audiomix_sel
> > > sels[]
> > > > > = {
> > > > > >         CLK_GATE("ocrama", OCRAMA_IPG),
> > > > > >         CLK_GATE("aud2htx", AUD2HTX_IPG),
> > > > > >         CLK_GATE("earc_phy", EARC_PHY),
> > > > > > -       CLK_GATE("sdma2", SDMA2_ROOT),
> > > > > >         CLK_GATE("sdma3", SDMA3_ROOT),
> > > > > >         CLK_GATE("spba2", SPBA2_ROOT),
> > > > > >         CLK_GATE("dsp", DSP_ROOT),
> > > > > > --
> > > > > > 2.37.1
> > > > > >
> > > > > >

[PATCH V3 06/15] clk: imx: imx8mp: fix clock tree update of TF-A managed clocks

[Peng Fan (OSS)]

From: Zhipeng Wang <zhipeng.wang_1@nxp.com>

On the i.MX8M*, the TF-A exposes a SiP (Silicon Provider) service
for DDR frequency scaling. The imx8m-ddrc-devfreq driver calls the
SiP and then does clk_set_parent on the DDR muxes to synchronize
the clock tree.

since commit 936c383673b9 ("clk: imx: fix composite peripheral flags"),
these TF-A managed muxes have SET_PARENT_GATE set, which results
in imx8m-ddrc-devfreq's clk_set_parent after SiP failing with -EBUSY:

clk_set_parent(dram_apb_src, sys1_pll_40m);(busfreq-imx8mq.c)

commit 926bf91248dd
("clk: imx8m: fix clock tree update of TF-A managed clocks") adds this
method and enables 8mm, 8mn and 8mq. i.MX8MP also needs it.

This is safe to do, because updating the Linux clock tree to reflect
reality will always be glitch-free.

Another reason to this patch is that powersave image BT music
requires dram to be 400MTS, so clk_set_parent(dram_alt_src,
sys1_pll_800m); is required. Without this patch, it will not succeed.

Fixes: 936c383673b9 ("clk: imx: fix composite peripheral flags")
Signed-off-by: Zhipeng Wang <zhipeng.wang_1@nxp.com>
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-imx8mp.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index 670aa2bab301..e561ff7b135f 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -551,8 +551,8 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
 
 	hws[IMX8MP_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb_root", ccm_base + 0x9080, 0, 1);
 
-	hws[IMX8MP_CLK_DRAM_ALT] = imx8m_clk_hw_composite("dram_alt", imx8mp_dram_alt_sels, ccm_base + 0xa000);
-	hws[IMX8MP_CLK_DRAM_APB] = imx8m_clk_hw_composite_critical("dram_apb", imx8mp_dram_apb_sels, ccm_base + 0xa080);
+	hws[IMX8MP_CLK_DRAM_ALT] = imx8m_clk_hw_fw_managed_composite("dram_alt", imx8mp_dram_alt_sels, ccm_base + 0xa000);
+	hws[IMX8MP_CLK_DRAM_APB] = imx8m_clk_hw_fw_managed_composite_critical("dram_apb", imx8mp_dram_apb_sels, ccm_base + 0xa080);
 	hws[IMX8MP_CLK_VPU_G1] = imx8m_clk_hw_composite("vpu_g1", imx8mp_vpu_g1_sels, ccm_base + 0xa100);
 	hws[IMX8MP_CLK_VPU_G2] = imx8m_clk_hw_composite("vpu_g2", imx8mp_vpu_g2_sels, ccm_base + 0xa180);
 	hws[IMX8MP_CLK_CAN1] = imx8m_clk_hw_composite("can1", imx8mp_can1_sels, ccm_base + 0xa200);
-- 
2.37.1

[PATCH V3 07/15] clk: imx: Remove CLK_SET_PARENT_GATE for DRAM mux for i.MX7D

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

For i.MX7D DRAM related mux clock, the clock source change should ONLY
be done done in low level asm code without accessing DRAM, and then
calling clk API to sync the HW clock status with clk tree, it should never
touch real clock source switch via clk API, so CLK_SET_PARENT_GATE flag
should NOT be added, otherwise, DRAM's clock parent will be disabled when
DRAM is active, and system will hang.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-imx7d.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index 2b77d1fc7bb9..1e1296e74835 100644
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -498,9 +498,9 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
 	hws[IMX7D_ENET_AXI_ROOT_SRC] = imx_clk_hw_mux2_flags("enet_axi_src", base + 0x8900, 24, 3, enet_axi_sel, ARRAY_SIZE(enet_axi_sel), CLK_SET_PARENT_GATE);
 	hws[IMX7D_NAND_USDHC_BUS_ROOT_SRC] = imx_clk_hw_mux2_flags("nand_usdhc_src", base + 0x8980, 24, 3, nand_usdhc_bus_sel, ARRAY_SIZE(nand_usdhc_bus_sel), CLK_SET_PARENT_GATE);
 	hws[IMX7D_DRAM_PHYM_ROOT_SRC] = imx_clk_hw_mux2_flags("dram_phym_src", base + 0x9800, 24, 1, dram_phym_sel, ARRAY_SIZE(dram_phym_sel), CLK_SET_PARENT_GATE);
-	hws[IMX7D_DRAM_ROOT_SRC] = imx_clk_hw_mux2_flags("dram_src", base + 0x9880, 24, 1, dram_sel, ARRAY_SIZE(dram_sel), CLK_SET_PARENT_GATE);
+	hws[IMX7D_DRAM_ROOT_SRC] = imx_clk_hw_mux2("dram_src", base + 0x9880, 24, 1, dram_sel, ARRAY_SIZE(dram_sel));
 	hws[IMX7D_DRAM_PHYM_ALT_ROOT_SRC] = imx_clk_hw_mux2_flags("dram_phym_alt_src", base + 0xa000, 24, 3, dram_phym_alt_sel, ARRAY_SIZE(dram_phym_alt_sel), CLK_SET_PARENT_GATE);
-	hws[IMX7D_DRAM_ALT_ROOT_SRC]  = imx_clk_hw_mux2_flags("dram_alt_src", base + 0xa080, 24, 3, dram_alt_sel, ARRAY_SIZE(dram_alt_sel), CLK_SET_PARENT_GATE);
+	hws[IMX7D_DRAM_ALT_ROOT_SRC]  = imx_clk_hw_mux2("dram_alt_src", base + 0xa080, 24, 3, dram_alt_sel, ARRAY_SIZE(dram_alt_sel));
 	hws[IMX7D_USB_HSIC_ROOT_SRC] = imx_clk_hw_mux2_flags("usb_hsic_src", base + 0xa100, 24, 3, usb_hsic_sel, ARRAY_SIZE(usb_hsic_sel), CLK_SET_PARENT_GATE);
 	hws[IMX7D_PCIE_CTRL_ROOT_SRC] = imx_clk_hw_mux2_flags("pcie_ctrl_src", base + 0xa180, 24, 3, pcie_ctrl_sel, ARRAY_SIZE(pcie_ctrl_sel), CLK_SET_PARENT_GATE);
 	hws[IMX7D_PCIE_PHY_ROOT_SRC] = imx_clk_hw_mux2_flags("pcie_phy_src", base + 0xa200, 24, 3, pcie_phy_sel, ARRAY_SIZE(pcie_phy_sel), CLK_SET_PARENT_GATE);
-- 
2.37.1

[PATCH V3 08/15] clk: imx: add CLK_SET_RATE_PARENT for lcdif_pixel_src for i.MX7D

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

Add flag 'CLK_SET_RATE_PARENT' to 'IMX7D_LCDIF_PIXEL_ROOT_SRC' to
propagate rate changes from LCDIF pixel clock to video PLL to
provide more accurate clock rate for LCDIF pixel clock.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-imx7d.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index 1e1296e74835..99adc55e3f5d 100644
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -505,7 +505,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
 	hws[IMX7D_PCIE_CTRL_ROOT_SRC] = imx_clk_hw_mux2_flags("pcie_ctrl_src", base + 0xa180, 24, 3, pcie_ctrl_sel, ARRAY_SIZE(pcie_ctrl_sel), CLK_SET_PARENT_GATE);
 	hws[IMX7D_PCIE_PHY_ROOT_SRC] = imx_clk_hw_mux2_flags("pcie_phy_src", base + 0xa200, 24, 3, pcie_phy_sel, ARRAY_SIZE(pcie_phy_sel), CLK_SET_PARENT_GATE);
 	hws[IMX7D_EPDC_PIXEL_ROOT_SRC] = imx_clk_hw_mux2_flags("epdc_pixel_src", base + 0xa280, 24, 3, epdc_pixel_sel, ARRAY_SIZE(epdc_pixel_sel), CLK_SET_PARENT_GATE);
-	hws[IMX7D_LCDIF_PIXEL_ROOT_SRC] = imx_clk_hw_mux2_flags("lcdif_pixel_src", base + 0xa300, 24, 3, lcdif_pixel_sel, ARRAY_SIZE(lcdif_pixel_sel), CLK_SET_PARENT_GATE);
+	hws[IMX7D_LCDIF_PIXEL_ROOT_SRC] = imx_clk_hw_mux2_flags("lcdif_pixel_src", base + 0xa300, 24, 3, lcdif_pixel_sel, ARRAY_SIZE(lcdif_pixel_sel), CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT);
 	hws[IMX7D_MIPI_DSI_ROOT_SRC] = imx_clk_hw_mux2_flags("mipi_dsi_src", base + 0xa380, 24, 3,  mipi_dsi_sel, ARRAY_SIZE(mipi_dsi_sel), CLK_SET_PARENT_GATE);
 	hws[IMX7D_MIPI_CSI_ROOT_SRC] = imx_clk_hw_mux2_flags("mipi_csi_src", base + 0xa400, 24, 3, mipi_csi_sel, ARRAY_SIZE(mipi_csi_sel), CLK_SET_PARENT_GATE);
 	hws[IMX7D_MIPI_DPHY_ROOT_SRC] = imx_clk_hw_mux2_flags("mipi_dphy_src", base + 0xa480, 24, 3, mipi_dphy_sel, ARRAY_SIZE(mipi_dphy_sel), CLK_SET_PARENT_GATE);
-- 
2.37.1

[PATCH V3 09/15] clk: imx: imx8mn: add sai7_ipg_clk clock settings

[Peng Fan (OSS)]

From: Adrian Alonso <adrian.alonso@nxp.com>

Add IMX8MN_CLK_SAI7_IPG clock entry.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-imx8mn.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index 4bd1ed11353b..ab77e148e70c 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -583,6 +583,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
 	hws[IMX8MN_CLK_SDMA2_ROOT] = imx_clk_hw_gate4("sdma2_clk", "ipg_audio_root", base + 0x43b0, 0);
 	hws[IMX8MN_CLK_SDMA3_ROOT] = imx_clk_hw_gate4("sdma3_clk", "ipg_audio_root", base + 0x45f0, 0);
 	hws[IMX8MN_CLK_SAI7_ROOT] = imx_clk_hw_gate2_shared2("sai7_root_clk", "sai7", base + 0x4650, 0, &share_count_sai7);
+	hws[IMX8MN_CLK_SAI7_IPG] = imx_clk_hw_gate2_shared2("sai7_ipg_clk", "ipg_audio_root", base + 0x4650, 0, &share_count_sai7);
 
 	hws[IMX8MN_CLK_GPT_3M] = imx_clk_hw_fixed_factor("gpt_3m", "osc_24m", 1, 8);
 
-- 
2.37.1

[PATCH V3 10/15] clk: imx: imx8mm: Change the 'nand_usdhc_bus' clock to non-critical one

[Peng Fan (OSS)]

From: Jacky Bai <ping.bai@nxp.com>

The 'nand_usdhc_bus' clock is only need to be enabled when usdhc
or nand module is active, so change it to non-critical clock type.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-imx8mm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 075f643e3f35..342049b847b9 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -432,7 +432,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
 	/* BUS */
 	hws[IMX8MM_CLK_MAIN_AXI] = imx8m_clk_hw_composite_bus_critical("main_axi",  imx8mm_main_axi_sels, base + 0x8800);
 	hws[IMX8MM_CLK_ENET_AXI] = imx8m_clk_hw_composite_bus("enet_axi", imx8mm_enet_axi_sels, base + 0x8880);
-	hws[IMX8MM_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite_bus_critical("nand_usdhc_bus", imx8mm_nand_usdhc_sels, base + 0x8900);
+	hws[IMX8MM_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite("nand_usdhc_bus", imx8mm_nand_usdhc_sels, base + 0x8900);
 	hws[IMX8MM_CLK_VPU_BUS] = imx8m_clk_hw_composite_bus("vpu_bus", imx8mm_vpu_bus_sels, base + 0x8980);
 	hws[IMX8MM_CLK_DISP_AXI] = imx8m_clk_hw_composite_bus("disp_axi", imx8mm_disp_axi_sels, base + 0x8a00);
 	hws[IMX8MM_CLK_DISP_APB] = imx8m_clk_hw_composite_bus("disp_apb", imx8mm_disp_apb_sels, base + 0x8a80);
-- 
2.37.1

[PATCH V3 11/15] clk: imx: imx8qxp: Add LVDS bypass clocks

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

For iMX8QXP and iMX8QM, add bypass clocks and register some of the LVDS
clocks with imx_clk_scu2 as the parent needs to explicitly set.

In order to make sure MIPI DSI works well after suspend/resume, the LVDS
pixel and phy clocks must be initialized before the MIPI tx_esacpe
and rx_escape clocks. LVDS phy, LVDS pixel, tx_escape, and rx_esacpe are all
on the same MSLICE. They all share the same clock parent. So, setting the
parent source or rate affects all of these clocks. In the LVDS use case the
MIPI tx_escape and rx_escape are not saved and restored. So, LVDS works for
either clock initialization order. For MIPI case, LVDS must be initialized first.

Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
Signed-off-by: "Oliver F. Brown" <oliver.brown@oss.nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-imx8qxp.c | 17 ++++++++---------
 1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
index 7d8883916cac..a0654edaae83 100644
--- a/drivers/clk/imx/clk-imx8qxp.c
+++ b/drivers/clk/imx/clk-imx8qxp.c
@@ -71,7 +71,7 @@ static const char *const lvds0_sels[] = {
 	"clk_dummy",
 	"clk_dummy",
 	"clk_dummy",
-	"mipi0_lvds_bypass_clk",
+	"lvds0_bypass_clk",
 };
 
 static const char *const lvds1_sels[] = {
@@ -79,7 +79,7 @@ static const char *const lvds1_sels[] = {
 	"clk_dummy",
 	"clk_dummy",
 	"clk_dummy",
-	"mipi1_lvds_bypass_clk",
+	"lvds1_bypass_clk",
 };
 
 static const char * const mipi_sels[] = {
@@ -223,9 +223,9 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
 	/* MIPI-LVDS SS */
 	imx_clk_scu("mipi0_bypass_clk", IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_BYPASS);
 	imx_clk_scu("mipi0_pixel_clk", IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PER);
-	imx_clk_scu("mipi0_lvds_bypass_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_BYPASS);
-	imx_clk_scu2("mipi0_lvds_pixel_clk", lvds0_sels, ARRAY_SIZE(lvds0_sels), IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2);
-	imx_clk_scu2("mipi0_lvds_phy_clk", lvds0_sels, ARRAY_SIZE(lvds0_sels), IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3);
+	imx_clk_scu("lvds0_bypass_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_BYPASS);
+	imx_clk_scu2("lvds0_pixel_clk", lvds0_sels, ARRAY_SIZE(lvds0_sels), IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2);
+	imx_clk_scu2("lvds0_phy_clk", lvds0_sels, ARRAY_SIZE(lvds0_sels), IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3);
 	imx_clk_scu2("mipi0_dsi_tx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_MST_BUS);
 	imx_clk_scu2("mipi0_dsi_rx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_SLV_BUS);
 	imx_clk_scu2("mipi0_dsi_phy_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PHY);
@@ -235,10 +235,9 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
 
 	imx_clk_scu("mipi1_bypass_clk", IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_BYPASS);
 	imx_clk_scu("mipi1_pixel_clk", IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_PER);
-	imx_clk_scu("mipi1_lvds_bypass_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_BYPASS);
-	imx_clk_scu2("mipi1_lvds_pixel_clk", lvds1_sels, ARRAY_SIZE(lvds1_sels), IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2);
-	imx_clk_scu2("mipi1_lvds_phy_clk", lvds1_sels, ARRAY_SIZE(lvds1_sels), IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3);
-
+	imx_clk_scu("lvds1_bypass_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_BYPASS);
+	imx_clk_scu2("lvds1_pixel_clk", lvds1_sels, ARRAY_SIZE(lvds1_sels), IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2);
+	imx_clk_scu2("lvds1_phy_clk", lvds1_sels, ARRAY_SIZE(lvds1_sels), IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3);
 	imx_clk_scu2("mipi1_dsi_tx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_MST_BUS);
 	imx_clk_scu2("mipi1_dsi_rx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_SLV_BUS);
 	imx_clk_scu2("mipi1_dsi_phy_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_PHY);
-- 
2.37.1

[PATCH V3 12/15] clk: imx: imx8qxp: Add clock muxes for MIPI and PHY ref clocks

[Peng Fan (OSS)]

From: "Oliver F. Brown" <oliver.brown@oss.nxp.com>

The MIPI Pixel and PHY Reference can use the bypass clock as a source. The
MIPI bypass clock is the Pixel clock from the Display controller via the
pixel link. Using the pixel clock for the PHY reference allows the MIPI bit
clock match the pixel rate exactly.

The MIPI pixel clock is currently set to be source from the bypass clock in
the SCFW. This patch allows the pixel clock parent to be set by the kernel
in the event that the SCFW default clock parent may change in the future.

Signed-off-by: "Oliver F. Brown" <oliver.brown@oss.nxp.com>
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-imx8qxp.c | 24 ++++++++++++++++++++----
 1 file changed, 20 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
index a0654edaae83..fe6509be6ce9 100644
--- a/drivers/clk/imx/clk-imx8qxp.c
+++ b/drivers/clk/imx/clk-imx8qxp.c
@@ -90,6 +90,22 @@ static const char * const mipi_sels[] = {
 	"clk_dummy",
 };
 
+static const char * const mipi0_phy_sels[] = {
+	"clk_dummy",
+	"clk_dummy",
+	"mipi_pll_div2_clk",
+	"clk_dummy",
+	"mipi0_bypass_clk",
+};
+
+static const char * const mipi1_phy_sels[] = {
+	"clk_dummy",
+	"clk_dummy",
+	"mipi_pll_div2_clk",
+	"clk_dummy",
+	"mipi1_bypass_clk",
+};
+
 static const char * const lcd_sels[] = {
 	"clk_dummy",
 	"clk_dummy",
@@ -222,25 +238,25 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
 
 	/* MIPI-LVDS SS */
 	imx_clk_scu("mipi0_bypass_clk", IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_BYPASS);
-	imx_clk_scu("mipi0_pixel_clk", IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PER);
+	imx_clk_scu2("mipi0_pixel_clk", mipi0_phy_sels, ARRAY_SIZE(mipi0_phy_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PER);
 	imx_clk_scu("lvds0_bypass_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_BYPASS);
 	imx_clk_scu2("lvds0_pixel_clk", lvds0_sels, ARRAY_SIZE(lvds0_sels), IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2);
 	imx_clk_scu2("lvds0_phy_clk", lvds0_sels, ARRAY_SIZE(lvds0_sels), IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3);
 	imx_clk_scu2("mipi0_dsi_tx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_MST_BUS);
 	imx_clk_scu2("mipi0_dsi_rx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_SLV_BUS);
-	imx_clk_scu2("mipi0_dsi_phy_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PHY);
+	imx_clk_scu2("mipi0_dsi_phy_clk", mipi0_phy_sels, ARRAY_SIZE(mipi0_phy_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PHY);
 	imx_clk_scu("mipi0_i2c0_clk", IMX_SC_R_MIPI_0_I2C_0, IMX_SC_PM_CLK_MISC2);
 	imx_clk_scu("mipi0_i2c1_clk", IMX_SC_R_MIPI_0_I2C_1, IMX_SC_PM_CLK_MISC2);
 	imx_clk_scu("mipi0_pwm0_clk", IMX_SC_R_MIPI_0_PWM_0, IMX_SC_PM_CLK_PER);
 
 	imx_clk_scu("mipi1_bypass_clk", IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_BYPASS);
-	imx_clk_scu("mipi1_pixel_clk", IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_PER);
+	imx_clk_scu2("mipi1_pixel_clk", mipi1_phy_sels, ARRAY_SIZE(mipi1_phy_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_PER);
 	imx_clk_scu("lvds1_bypass_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_BYPASS);
 	imx_clk_scu2("lvds1_pixel_clk", lvds1_sels, ARRAY_SIZE(lvds1_sels), IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2);
 	imx_clk_scu2("lvds1_phy_clk", lvds1_sels, ARRAY_SIZE(lvds1_sels), IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3);
 	imx_clk_scu2("mipi1_dsi_tx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_MST_BUS);
 	imx_clk_scu2("mipi1_dsi_rx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_SLV_BUS);
-	imx_clk_scu2("mipi1_dsi_phy_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_PHY);
+	imx_clk_scu2("mipi1_dsi_phy_clk", mipi1_phy_sels, ARRAY_SIZE(mipi1_phy_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_PHY);
 	imx_clk_scu("mipi1_i2c0_clk", IMX_SC_R_MIPI_1_I2C_0, IMX_SC_PM_CLK_MISC2);
 	imx_clk_scu("mipi1_i2c1_clk", IMX_SC_R_MIPI_1_I2C_1, IMX_SC_PM_CLK_MISC2);
 	imx_clk_scu("mipi1_pwm0_clk", IMX_SC_R_MIPI_1_PWM_0, IMX_SC_PM_CLK_PER);
-- 
2.37.1

[PATCH V3 13/15] clk: imx: imx8qxp: Register dc0_bypass0_clk before disp clk

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

The initialization order of SCU clocks affects the sequence of SCU clock
resume. If there are no other effects, the earlier the initialization,
the earlier the resume. During SCU clock resume, the clock rate is
restored. As SCFW guidelines, configure the parent clock rate before
configuring the child rate.

Fixes: 91e916771de0 ("clk: imx: scu: remove legacy scu clock binding support")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-imx8qxp.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
index fe6509be6ce9..47f4ceab1179 100644
--- a/drivers/clk/imx/clk-imx8qxp.c
+++ b/drivers/clk/imx/clk-imx8qxp.c
@@ -222,11 +222,11 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
 	imx_clk_scu("usb3_lpm_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MISC);
 
 	/* Display controller SS */
-	imx_clk_scu2("dc0_disp0_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC0);
-	imx_clk_scu2("dc0_disp1_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1);
 	imx_clk_scu("dc0_pll0_clk", IMX_SC_R_DC_0_PLL_0, IMX_SC_PM_CLK_PLL);
 	imx_clk_scu("dc0_pll1_clk", IMX_SC_R_DC_0_PLL_1, IMX_SC_PM_CLK_PLL);
 	imx_clk_scu("dc0_bypass0_clk", IMX_SC_R_DC_0_VIDEO0, IMX_SC_PM_CLK_BYPASS);
+	imx_clk_scu2("dc0_disp0_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC0);
+	imx_clk_scu2("dc0_disp1_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1);
 	imx_clk_scu("dc0_bypass1_clk", IMX_SC_R_DC_0_VIDEO1, IMX_SC_PM_CLK_BYPASS);
 
 	imx_clk_scu2("dc1_disp0_clk", dc1_sels, ARRAY_SIZE(dc1_sels), IMX_SC_R_DC_1, IMX_SC_PM_CLK_MISC0);
-- 
2.37.1

[PATCH V3 14/15] clk: imx: imx8qxp: Parent should be initialized earlier than the clock

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

The initialization order of SCU clocks affects the sequence of SCU clock
resume. If there are no other effects, the earlier the initialization,
the earlier the resume. During SCU clock resume, the clock rate is
restored. As SCFW guidelines, configure the parent clock rate before
configuring the child rate.

Fixes: babfaa9556d7 ("clk: imx: scu: add more scu clocks")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-imx8qxp.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
index 47f4ceab1179..3ae162625bb1 100644
--- a/drivers/clk/imx/clk-imx8qxp.c
+++ b/drivers/clk/imx/clk-imx8qxp.c
@@ -186,8 +186,8 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
 	imx_clk_scu("pwm_clk",   IMX_SC_R_LCD_0_PWM_0, IMX_SC_PM_CLK_PER);
 	imx_clk_scu("elcdif_pll", IMX_SC_R_ELCDIF_PLL, IMX_SC_PM_CLK_PLL);
 	imx_clk_scu2("lcd_clk", lcd_sels, ARRAY_SIZE(lcd_sels), IMX_SC_R_LCD_0, IMX_SC_PM_CLK_PER);
-	imx_clk_scu2("lcd_pxl_clk", lcd_pxl_sels, ARRAY_SIZE(lcd_pxl_sels), IMX_SC_R_LCD_0, IMX_SC_PM_CLK_MISC0);
 	imx_clk_scu("lcd_pxl_bypass_div_clk", IMX_SC_R_LCD_0, IMX_SC_PM_CLK_BYPASS);
+	imx_clk_scu2("lcd_pxl_clk", lcd_pxl_sels, ARRAY_SIZE(lcd_pxl_sels), IMX_SC_R_LCD_0, IMX_SC_PM_CLK_MISC0);
 
 	/* Audio SS */
 	imx_clk_scu("audio_pll0_clk", IMX_SC_R_AUDIO_PLL_0, IMX_SC_PM_CLK_PLL);
@@ -229,11 +229,11 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
 	imx_clk_scu2("dc0_disp1_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1);
 	imx_clk_scu("dc0_bypass1_clk", IMX_SC_R_DC_0_VIDEO1, IMX_SC_PM_CLK_BYPASS);
 
-	imx_clk_scu2("dc1_disp0_clk", dc1_sels, ARRAY_SIZE(dc1_sels), IMX_SC_R_DC_1, IMX_SC_PM_CLK_MISC0);
-	imx_clk_scu2("dc1_disp1_clk", dc1_sels, ARRAY_SIZE(dc1_sels), IMX_SC_R_DC_1, IMX_SC_PM_CLK_MISC1);
 	imx_clk_scu("dc1_pll0_clk", IMX_SC_R_DC_1_PLL_0, IMX_SC_PM_CLK_PLL);
 	imx_clk_scu("dc1_pll1_clk", IMX_SC_R_DC_1_PLL_1, IMX_SC_PM_CLK_PLL);
 	imx_clk_scu("dc1_bypass0_clk", IMX_SC_R_DC_1_VIDEO0, IMX_SC_PM_CLK_BYPASS);
+	imx_clk_scu2("dc1_disp0_clk", dc1_sels, ARRAY_SIZE(dc1_sels), IMX_SC_R_DC_1, IMX_SC_PM_CLK_MISC0);
+	imx_clk_scu2("dc1_disp1_clk", dc1_sels, ARRAY_SIZE(dc1_sels), IMX_SC_R_DC_1, IMX_SC_PM_CLK_MISC1);
 	imx_clk_scu("dc1_bypass1_clk", IMX_SC_R_DC_1_VIDEO1, IMX_SC_PM_CLK_BYPASS);
 
 	/* MIPI-LVDS SS */
-- 
2.37.1

[PATCH V3 15/15] clk: imx: fracn-gppll: update rate table

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

- Add 1039.5MHz clock for video PLL to fulfill the LVDS display
  148.5MHz * 7 requirement
- Add 800MHz clock for ARM PLL

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-fracn-gppll.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c
index 1becba2b62d0..591e0364ee5c 100644
--- a/drivers/clk/imx/clk-fracn-gppll.c
+++ b/drivers/clk/imx/clk-fracn-gppll.c
@@ -78,6 +78,7 @@ struct clk_fracn_gppll {
  * The Fvco should be in range 2.5Ghz to 5Ghz
  */
 static const struct imx_fracn_gppll_rate_table fracn_tbl[] = {
+	PLL_FRACN_GP(1039500000U, 173, 25, 100, 1, 4),
 	PLL_FRACN_GP(650000000U, 162, 50, 100, 0, 6),
 	PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8),
 	PLL_FRACN_GP(560000000U, 140, 0, 1, 0, 6),
@@ -106,6 +107,7 @@ static const struct imx_fracn_gppll_rate_table int_tbl[] = {
 	PLL_FRACN_GP_INTEGER(1700000000U, 141, 1, 2),
 	PLL_FRACN_GP_INTEGER(1400000000U, 175, 1, 3),
 	PLL_FRACN_GP_INTEGER(900000000U, 150, 1, 4),
+	PLL_FRACN_GP_INTEGER(800000000U, 200, 1, 6),
 };
 
 struct imx_fracn_gppll_clk imx_fracn_gppll_integer = {
-- 
2.37.1

RE: [PATCH V3 00/15] clk: imx: misc update/fix

[Peng Fan]

Hi Abel,

> Subject: [PATCH V3 00/15] clk: imx: misc update/fix

Would you give a look on this patchset?

Thanks,
Peng.

> 
> From: Peng Fan <peng.fan@nxp.com>
> 
> Changes in v3:
> - Drop two patches
>       clk: imx: pll14xx: Add constraint for fvco frequency
>       clk: imx: pll14xx: use rate_table for audio plls
> - Update 8ULP PCC check to not return Error
> - Update commit log and Add R-b for
>   "clk: imx: imx8mp: fix clock tree update of TF-A managed clocks"
> - Link to v2: https://lore.kernel.org/all/20240510-imx-clk-v2-0-
> c998f315d29c@nxp.com/
> 
> 
> Changes in v2:
> - Drop "clk: imx: pll14xx: potential integer overflow eliminated by
>        casting to u64"
> - Add Fixes tag  "clk: imx: imx8mp-audiomix: remove sdma root clock"
> - Link to v1: https://lore.kernel.org/r/20240504-imx-clk-v1-0-
> f7915489d58d@nxp.com
> 
> Upstream several patches landed in NXP downstream repo for some
> time.
> - i.MX8M/93/7ULP composite clk update
> - Fix Fracn-gppll MFN got lost
> - PLL14xx update
> - i.MX8MP DRAM CLK fix
> - i.MX8MM/N misc update
> - Init i.MX8QXP parent clk before child clk
> 
> Downstream tags are kept for the patches got R-b
> 
> Although there are a few fixes, non-urgent for 6.10.
> 
> Adrian Alonso (1):
>   clk: imx: imx8mn: add sai7_ipg_clk clock settings
> 
> Jacky Bai (2):
>   clk: imx: composite-93: keep root clock on when mcore enabled
>   clk: imx: imx8mm: Change the 'nand_usdhc_bus' clock to non-critical
>     one
> 
> Oliver F. Brown (1):
>   clk: imx: imx8qxp: Add clock muxes for MIPI and PHY ref clocks
> 
> Peng Fan (8):
>   clk: imx: composite-8m: Enable gate clk with mcore_booted
>   clk: imx: imx8mp-audiomix: remove sdma root clock
>   clk: imx: Remove CLK_SET_PARENT_GATE for DRAM mux for i.MX7D
>   clk: imx: add CLK_SET_RATE_PARENT for lcdif_pixel_src for i.MX7D
>   clk: imx: imx8qxp: Add LVDS bypass clocks
>   clk: imx: imx8qxp: Register dc0_bypass0_clk before disp clk
>   clk: imx: imx8qxp: Parent should be initialized earlier than the clock
>   clk: imx: fracn-gppll: update rate table
> 
> Pengfei Li (1):
>   clk: imx: fracn-gppll: fix fractional part of PLL getting lost
> 
> Ye Li (1):
>   clk: imx: composite-7ulp: Check the PCC present bit
> 
> Zhipeng Wang (1):
>   clk: imx: imx8mp: fix clock tree update of TF-A managed clocks
> 
>  drivers/clk/imx/clk-composite-7ulp.c  |  7 ++++
>  drivers/clk/imx/clk-composite-8m.c    | 53 +++++++++++++++++++++----
> --
>  drivers/clk/imx/clk-composite-93.c    | 15 ++++----
>  drivers/clk/imx/clk-fracn-gppll.c     |  6 +++
>  drivers/clk/imx/clk-imx7d.c           |  6 +--
>  drivers/clk/imx/clk-imx8mm.c          |  2 +-
>  drivers/clk/imx/clk-imx8mn.c          |  1 +
>  drivers/clk/imx/clk-imx8mp-audiomix.c |  1 -
>  drivers/clk/imx/clk-imx8mp.c          |  4 +-
>  drivers/clk/imx/clk-imx8qxp.c         | 51 +++++++++++++++++---------
>  10 files changed, 103 insertions(+), 43 deletions(-)
> 
> --
> 2.37.1

Re: [PATCH V3 00/15] clk: imx: misc update/fix

[Abel Vesa]

On 24-06-07 21:33:32, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
> 

Whole series LGTM.

Reviewed-by: Abel Vesa <abel.vesa@linaro.org>


> Changes in v3:
> - Drop two patches
>       clk: imx: pll14xx: Add constraint for fvco frequency
>       clk: imx: pll14xx: use rate_table for audio plls
> - Update 8ULP PCC check to not return Error
> - Update commit log and Add R-b for 
>   "clk: imx: imx8mp: fix clock tree update of TF-A managed clocks"
> - Link to v2: https://lore.kernel.org/all/20240510-imx-clk-v2-0-c998f315d29c@nxp.com/
> 
> 
> Changes in v2:
> - Drop "clk: imx: pll14xx: potential integer overflow eliminated by
>        casting to u64"
> - Add Fixes tag  "clk: imx: imx8mp-audiomix: remove sdma root clock"
> - Link to v1: https://lore.kernel.org/r/20240504-imx-clk-v1-0-f7915489d58d@nxp.com
> 
> Upstream several patches landed in NXP downstream repo for some time.
> - i.MX8M/93/7ULP composite clk update
> - Fix Fracn-gppll MFN got lost
> - PLL14xx update
> - i.MX8MP DRAM CLK fix
> - i.MX8MM/N misc update
> - Init i.MX8QXP parent clk before child clk
> 
> Downstream tags are kept for the patches got R-b
> 
> Although there are a few fixes, non-urgent for 6.10.
> 
> Adrian Alonso (1):
>   clk: imx: imx8mn: add sai7_ipg_clk clock settings
> 
> Jacky Bai (2):
>   clk: imx: composite-93: keep root clock on when mcore enabled
>   clk: imx: imx8mm: Change the 'nand_usdhc_bus' clock to non-critical
>     one
> 
> Oliver F. Brown (1):
>   clk: imx: imx8qxp: Add clock muxes for MIPI and PHY ref clocks
> 
> Peng Fan (8):
>   clk: imx: composite-8m: Enable gate clk with mcore_booted
>   clk: imx: imx8mp-audiomix: remove sdma root clock
>   clk: imx: Remove CLK_SET_PARENT_GATE for DRAM mux for i.MX7D
>   clk: imx: add CLK_SET_RATE_PARENT for lcdif_pixel_src for i.MX7D
>   clk: imx: imx8qxp: Add LVDS bypass clocks
>   clk: imx: imx8qxp: Register dc0_bypass0_clk before disp clk
>   clk: imx: imx8qxp: Parent should be initialized earlier than the clock
>   clk: imx: fracn-gppll: update rate table
> 
> Pengfei Li (1):
>   clk: imx: fracn-gppll: fix fractional part of PLL getting lost
> 
> Ye Li (1):
>   clk: imx: composite-7ulp: Check the PCC present bit
> 
> Zhipeng Wang (1):
>   clk: imx: imx8mp: fix clock tree update of TF-A managed clocks
> 
>  drivers/clk/imx/clk-composite-7ulp.c  |  7 ++++
>  drivers/clk/imx/clk-composite-8m.c    | 53 +++++++++++++++++++++------
>  drivers/clk/imx/clk-composite-93.c    | 15 ++++----
>  drivers/clk/imx/clk-fracn-gppll.c     |  6 +++
>  drivers/clk/imx/clk-imx7d.c           |  6 +--
>  drivers/clk/imx/clk-imx8mm.c          |  2 +-
>  drivers/clk/imx/clk-imx8mn.c          |  1 +
>  drivers/clk/imx/clk-imx8mp-audiomix.c |  1 -
>  drivers/clk/imx/clk-imx8mp.c          |  4 +-
>  drivers/clk/imx/clk-imx8qxp.c         | 51 +++++++++++++++++---------
>  10 files changed, 103 insertions(+), 43 deletions(-)
> 
> -- 
> 2.37.1
> 

Re: [PATCH V3 00/15] clk: imx: misc update/fix

[Abel Vesa]

On Fri, 07 Jun 2024 21:33:32 +0800, Peng Fan (OSS) wrote:
> Changes in v3:
> - Drop two patches
>       clk: imx: pll14xx: Add constraint for fvco frequency
>       clk: imx: pll14xx: use rate_table for audio plls
> - Update 8ULP PCC check to not return Error
> - Update commit log and Add R-b for
>   "clk: imx: imx8mp: fix clock tree update of TF-A managed clocks"
> - Link to v2: https://lore.kernel.org/all/20240510-imx-clk-v2-0-c998f315d29c@nxp.com/
> 
> [...]

Applied, thanks!

[01/15] clk: imx: composite-8m: Enable gate clk with mcore_booted
        commit: b4c91df8118b5d4efdc9732206de81ac620f53d2
[02/15] clk: imx: composite-93: keep root clock on when mcore enabled
        commit: 90d91ce8e20e0df9806ce7f7c49f8ef05471b5ce
[03/15] clk: imx: composite-7ulp: Check the PCC present bit
        commit: afd1247ce838b4a06fb0c24e522687475583035d
[04/15] clk: imx: fracn-gppll: fix fractional part of PLL getting lost
        commit: af218f2d935e118582d43cbd89c81ef6f26be286
[05/15] clk: imx: imx8mp-audiomix: remove sdma root clock
        (no commit info)
[06/15] clk: imx: imx8mp: fix clock tree update of TF-A managed clocks
        commit: 6bc3d1e264ad5bace5d1980997abcc7ad5308181
[07/15] clk: imx: Remove CLK_SET_PARENT_GATE for DRAM mux for i.MX7D
        commit: 68a3e49a2a5e75a2e1511ff75ca24b584a0f12f4
[08/15] clk: imx: add CLK_SET_RATE_PARENT for lcdif_pixel_src for i.MX7D
        commit: e2d956067b0b3c9a9ba5acde655bf6fc708c3ab0
[09/15] clk: imx: imx8mn: add sai7_ipg_clk clock settings
        commit: 40cfc8c2fccf5440fb192aa80a84bff9f3288b2c
[10/15] clk: imx: imx8mm: Change the 'nand_usdhc_bus' clock to non-critical one
        commit: c7f85fc3dc2facacc1851db992d485a89acde8ee
[11/15] clk: imx: imx8qxp: Add LVDS bypass clocks
        commit: ecee2c870be1776c483b3d1a40e3998c7cb7eb1b
[12/15] clk: imx: imx8qxp: Add clock muxes for MIPI and PHY ref clocks
        commit: 385e7c90bdb571677c4d16d97e8809427dc4d8d7
[13/15] clk: imx: imx8qxp: Register dc0_bypass0_clk before disp clk
        commit: 9cf2310e4845006f72c959d38bd1300863432194
[14/15] clk: imx: imx8qxp: Parent should be initialized earlier than the clock
        commit: c69e0dba43e63862ec95cbd91a2daa28e3e87a9e
[15/15] clk: imx: fracn-gppll: update rate table
        commit: 747cf5fbfc4326ab2ad9cc73cde8eb7776f3ba53

Best regards,
-- 
Abel Vesa <abel.vesa@linaro.org>