Re: [PATCH v3 2/6] phy: exynos5-usbdrd: support isolating HS and SS ports independently

Peter Griffin
2024-06-24T11:20:38Z

Hi André,

On Mon, 17 Jun 2024 at 17:45, André Draszik <andre.draszik@linaro.org> wrote:
>
> Some versions of this IP have been integrated using separate PMU power
> control registers for the HS and SS parts. One example is the Google
> Tensor gs101 SoC.
>
> Such SoCs can now set pmu_offset_usbdrd0_phy_ss in their
> exynos5_usbdrd_phy_drvdata for the SS phy to the appropriate value.
>
> The existing 'usbdrdphy' alias can not be used in this case because
> that is meant for determining the correct PMU offset if multiple
> distinct PHYs exist in the system (as opposed to one PHY with multiple
> isolators).
>
> Signed-off-by: André Draszik <andre.draszik@linaro.org>
>
> ---

Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
and
Tested-by: Peter Griffin <peter.griffin@linaro.org>

Tested using my Pixel 6 pro device. USB comes up and it is possible to
use adb from the host to the phone

regards,

Peter

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