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AJvYcCW8xFKBJ9RTHCnntudM5Y2WAZqWR/GuAFe8cTfH0dMHyw/zEaLWojeJyBNeRJ/QLqv+mGBctmG1caSu/rPMmRlLxL9FyuNogM8Ausrh X-Gm-Message-State: AOJu0YytLggEi9C55yTnHl5B6r7jvxKxEb2d0PRhOGPwohfj+6BqZZ9j myx3t5fKyUABKwzdznqgA8w4XGnwSMfQaP5ZrgkKb42KY7E2A2u7oD0b6vqIe/dwmvgcGc25HRt QsA== X-Google-Smtp-Source: AGHT+IHIj7Frqqn9vAIzHqtf502PiSXlpH0diSrPuQbhr/RJ6vdXrfi41gkE/7i/gmNkhPd0gOtvr19TZbE= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a17:90a:a412:b0:2c9:6abb:ee40 with SMTP id 98e67ed59e1d1-2ca35d524b8mr13373a91.6.1720626144135; Wed, 10 Jul 2024 08:42:24 -0700 (PDT) Date: Wed, 10 Jul 2024 08:42:22 -0700 In-Reply-To: <5354a7ae-ca32-42fe-9231-a0d955bc8675@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <171961507216.241377.3829798983563243860.b4-ty@google.com> <5354a7ae-ca32-42fe-9231-a0d955bc8675@intel.com> Message-ID: Subject: Re: [PATCH V9 0/2] KVM: x86: Make bus clock frequency for vAPIC timer configurable From: Sean Christopherson To: Reinette Chatre Cc: isaku.yamahata@intel.com, pbonzini@redhat.com, erdemaktas@google.com, vkuznets@redhat.com, vannapurve@google.com, jmattson@google.com, mlevitsk@redhat.com, xiaoyao.li@intel.com, chao.gao@intel.com, rick.p.edgecombe@intel.com, yuan.yao@intel.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="us-ascii" On Fri, Jun 28, 2024, Reinette Chatre wrote: > Hi Sean, > > On 6/28/24 3:55 PM, Sean Christopherson wrote: > > On Wed, 12 Jun 2024 11:16:10 -0700, Reinette Chatre wrote: > > > Changes from v8: > > > - v8: https://lore.kernel.org/lkml/cover.1718043121.git.reinette.chatre@intel.com/ > > > - Many changes to new udelay() utility patch as well as the APIC bus > > > frequency test aimed to make it more robust (additional ASSERTs, > > > consistent types, eliminate duplicate code, etc.) and useful with > > > support for more user configuration. Please refer to individual patches for > > > detailed changes. > > > - Series applies cleanly to next branch of kvm-x86 with HEAD > > > e4e9e1067138e5620cf0500c3e5f6ebfb9d322c8. > > > > > > [...] > > > > Applied to kvm-x86 misc, with all the changes mentioned in my earlier replies. > > I'm out next week, and don't want to merge the KVM changes without these tests, > > hence the rushed application. > > > > Please holler if you disagree with anything (or if I broke something). I won't > > respond until July 8th at the earliest, but worst case scenario we can do fixup > > patches after 6.11-rc1. > > Thank you very much for taking the time to make the changes and apply the patches. > All the changes look good to me and passes my testing. > > Now that the x86 udelay() utility no longer use cpu_relax(), should ARM > and RISC-V's udelay() be modified to match in this regard? I can prepare > (unable to test) changes for you to consider on your return. I don't think so? IIUC, arm64's "yield", used by cpu_relax() doesn't trigger the "on spin" exists. Such exist are only triggered by "wfet" and friends.