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From: Ashok Raj <ashok.raj@intel.com>
To: Dave Hansen <dave.hansen@intel.com>
Cc: "Chang S. Bae" <chang.seok.bae@intel.com>,
	<linux-kernel@vger.kernel.org>, <x86@kernel.org>,
	<tglx@linutronix.de>, <mingo@redhat.com>, <bp@alien8.de>,
	<dave.hansen@linux.intel.com>, <tony.luck@intel.com>,
	Yan Hua Wu <yanhua1.wu@intel.com>,
	William Xie <william.xie@intel.com>,
	Ashok Raj <ashok.raj@intel.com>
Subject: Re: [PATCH 1/1] arch/x86/microcode/intel: Remove unnecessary cache writeback and invalidation
Date: Wed, 3 Jul 2024 14:33:58 -0700	[thread overview]
Message-ID: <ZoXDxldNlTYRo-0h@a4bf019067fa.jf.intel.com> (raw)
In-Reply-To: <bd0b19e8-ff72-4a6b-9f7f-400ddafddacd@intel.com>

On Wed, Jul 03, 2024 at 02:11:34PM -0700, Dave Hansen wrote:
> On 7/3/24 14:03, Ashok Raj wrote:
> > On Wed, Jul 03, 2024 at 01:55:19PM -0700, Dave Hansen wrote:
> >> On 7/3/24 13:50, Ashok Raj wrote:
> >>> Agree that we must get wider testing. Only caveat is that you should find a
> >>> newer microcode to apply, which might be difficult for all products. Unless
> >>> there is a debug option to reload force the same rev in case you don't have
> >>> a newer ucode to test. Its good to get this in to reduce the big hammer
> >>> effect.
> >>
> >> Why is it hard to find a newer microcode to apply?  Just because the
> >> BIOS-provided one is more likely to be the last update the other the CPU?
> > 
> > Yes, sometimes that, or an earlier update has already been applied via
> > early loading (which seems most of the case). Someone needs to do some
> > extra work to remove it from initramfs copy, reboot and redo the test.
> 
> This patch touches __apply_microcode(), which looks like it's used in
> both early and late loading.

In the old days we had a separate function for early and separate for late
loading. tglx consolidated them, so they all look pretty now. 

When wbinvd() was introduced I do believe we added to both early and late.
Although I don't recall entirely.

> 
> But it sounds like you're thinking that the WBINVD is (or was) primarily
> useful during late loading.  Why is that?
> 
> Or am I totally misreading the code again? :)

-- 
Cheers,
Ashok

  reply	other threads:[~2024-07-03 21:34 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-07-01 21:20 [PATCH 0/1] x86/microcode: Revert cache flush on Intel microcode loading Chang S. Bae
2024-07-01 21:20 ` [PATCH 1/1] arch/x86/microcode/intel: Remove unnecessary cache writeback and invalidation Chang S. Bae
2024-07-01 22:56   ` Dave Hansen
2024-07-03 20:50     ` Ashok Raj
2024-07-03 20:55       ` Dave Hansen
2024-07-03 21:03         ` Ashok Raj
2024-07-03 21:11           ` Dave Hansen
2024-07-03 21:33             ` Ashok Raj [this message]
2024-07-04  0:05               ` Chang S. Bae
2024-07-02 23:24   ` Chang S. Bae
2024-09-10 18:35   ` Chang S. Bae

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