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AJvYcCUz6e+eXzk3sIArXhRVojNy5uZ53aotdC8u/4RjVr/WiKVhxZD4dz6Y42WkZf9nqdwXGZjLvhnn+Wlm1cdMfYSVhIIB8H0Az3ToThVc X-Gm-Message-State: AOJu0YxdPtjcswfl+oLE+h1msvAAJ62vLIoBymgE8HkGckO8LjtaLzzX lAaeLvwWXToybb6kG9/FmiKqNMTvQJWvG4pajotQIoJDhjyQZq7yucv9rKhHEOTRfTReLg/xUc7 4IA== X-Google-Smtp-Source: AGHT+IHOyNGBl0lTxCv1pGrwQOW9eslx0DzywsCu/KV//UKtHQ2KhGiXtjHiSMZdzddUzk4dGaKgMyPOW3Q= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a63:bd4a:0:b0:785:e3e:38d3 with SMTP id 41be03b00d2f7-7b74853d441mr28660a12.7.1722893754549; Mon, 05 Aug 2024 14:35:54 -0700 (PDT) Date: Mon, 5 Aug 2024 14:35:53 -0700 In-Reply-To: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240517173926.965351-1-seanjc@google.com> <20240517173926.965351-25-seanjc@google.com> <20d3017a8dd54b345104bf2e5cb888a22a1e0a53.camel@redhat.com> <31cf77d34fc49735e6dff57344a0e532e028a975.camel@redhat.com> Message-ID: Subject: Re: [PATCH v2 24/49] KVM: x86: #undef SPEC_CTRL_SSBD in cpuid.c to avoid macro collisions From: Sean Christopherson To: mlevitsk@redhat.com Cc: Paolo Bonzini , Vitaly Kuznetsov , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Hou Wenlong , Kechen Lu , Oliver Upton , Binbin Wu , Yang Weijiang , Robert Hoo , Borislav Petkov Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable +Boris On Mon, Aug 05, 2024, mlevitsk@redhat.com wrote: > =D0=A3 =D0=BF=D1=82, 2024-07-26 =D1=83 16:34 -0700, Sean Christopherson = =D0=BF=D0=B8=D1=88=D0=B5: > > > On Wed, Jul 24, 2024, Maxim Levitsky wrote: > > > > > On Mon, 2024-07-08 at 14:29 -0700, Sean Christopherson wrote: > > > > > > > On Thu, Jul 04, 2024, Maxim Levitsky wrote: > > > > > > > > > Maybe we should instead rename the SPEC_CTRL_SSBD to > > > > > > > > > 'MSR_IA32_SPEC_CTRL_SSBD' and together with it, other fie= lds of this msr.=C2=A0 It > > > > > > > > > seems that at least some msrs in this file do this. > > > > > > >=20 > > > > > > > Yeah, the #undef hack is quite ugly.=C2=A0 But I didn't (and = still don't) want to > > > > > > > introduce all the renaming churn in the middle of this alread= y too-big series, > > > > > > > especially since it would require touching quite a bit of cod= e outside of KVM. > > > > >=20 > > > > > > >=20 > > > > > > > I'm also not sure that's the right thing to do; I kinda feel = like KVM is the one > > > > > > > that's being silly here. > > > > >=20 > > > > > I don't think that KVM is silly here. I think that hardware defin= itions like > > > > > MSRs, register names, register bit fields, etc, *must* come with = a unique > > > > > prefix, it's not an issue of breaking some deeply nested macro, b= ut rather an > > > > > issue of readability. > > >=20 > > > For the MSR names themselves, yes, I agree 100%.=C2=A0 But for the bi= ts and mask, I > > > disagree.=C2=A0 It's simply too verbose, especially given that in the= vast majority > > > of cases simply looking at the surrounding code will provide enough c= ontext to > > > glean an understanding of what's going on. >=20 > I am not that sure about this, especially if someone by mistake uses a fl= ag > that belong to one MSR, in some unrelated place. Verbose code is rarely a= bad thing. >=20 >=20 > > > =C2=A0 E.g. even for SPEC_CTRL_SSBD, where > > > there's an absurd amount of magic and layering, looking at the #defin= e makes > > > it fairly obvious that it belongs to MSR_IA32_SPEC_CTRL. > > >=20 > > > And for us x86 folks, who obviously look at this code far more often = than non-x86 > > > folks, I find it valuable to know that a bit/mask is exactly that, an= d _not_ an > > > MSR index.=C2=A0 E.g. VMX_BASIC_TRUE_CTLS is a good example, where re= naming that to > > > MSR_VMX_BASIC_TRUE_CTLS would make it look too much like MSR_IA32_VMX= _TRUE_ENTRY_CTLS > > > and all the other "true" VMX MSRs. > > >=20 > > > > > SPEC_CTRL_SSBD for example won't mean much to someone who only kn= ows ARM, while > > > > > MSR_SPEC_CTRL_SSBD, or even better IA32_MSR_SPEC_CTRL_SSBD, lets = you instantly know > > > > > that this is a MSR, and anyone with even a bit of x86 knowledge s= hould at least have > > > > > heard about what a MSR is. > > > > >=20 > > > > > In regard to X86_FEATURE_INTEL_SSBD, I don't oppose this idea, be= cause we have > > > > > X86_FEATURE_AMD_SSBD, but in general I do oppose the idea of addi= ng 'INTEL' prefix, > > >=20 > > > Ya, those are my feelings exactly.=C2=A0 And in this case, since we a= lready have an > > > AMD variant, I think it's actually a net positive to add an INTEL var= iant so that > > > it's clear that Intel and AMD ended up defining separate CPUID to enu= merate the > > > same basic info. > > >=20 > > > > > because it sets a not that good precedent, because most of the fe= atures on x86 > > > > > are first done by Intel, but then are also implemented by AMD, an= d thus an intel-only > > > > > feature name can stick after it becomes a general x86 feature. > > > > >=20 > > > > > IN case of X86_FEATURE_INTEL_SSBD, we already have sadly differen= t CPUID bits for > > > > > each vendor (although I wonder if AMD also sets the X86_FEATURE_I= NTEL_SSBD). > > > > >=20 > > > > > I vote to rename 'SPEC_CTRL_SSBD', it can be done as a standalone= patch, and can > > > > > be accepted right now, even before this patch series is accepted. > > >=20 > > > If we go that route, then we also need to rename nearly ever bit/mask= definition > > > in msr-index.h, otherwise SPEC_CTRL_* will be the odd ones out.=C2=A0= And as above, I > > > don't think this is the right direction. >=20 > Honestly not really. If you look carefully at the file, many bits are alr= eady defined > in the way I suggest, for example: >=20 > MSR_PLATFORM_INFO_CPUID_FAULT_BIT > MSR_IA32_POWER_CTL_BIT_EE > MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT > MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT Heh, I know there are some bits that have an "MSR" prefix, hence "nearly ev= ery". > This file has all kind of names for both msrs and flags. There is not muc= h > order, so renaming the bit definitions of IA32_SPEC_CTRL won't increase t= he > level of disorder in this file IMHO. It depends on what direction msr-index.h is headed. If the long-term prefe= rence is to have bits/masks namespaced with only their associated MSR name, i.e. = no explicit MSR_, then renaming the bits is counter-productive. I added Boris, who I believe was the most opinionated about the MSR bit nam= es, i.e. who can most likely give us the closest thing to an authoritative answ= er as to the preferred style. Boris, we're debating about the best way to solve a weird collision between= : #define SPEC_CTRL_SSBD and #define X86_FEATURE_SPEC_CTRL_SSBD KVM wants to use its CPUID macros to essentially do: #define F(name) (X86_FEATURE_##name) as a shorthand for X86_FEATURE_SPEC_CTRL_SSBD, but that can cause build fai= lures depending on how KVM's macros are layered. E.g. SPEC_CTRL_SSBD can get res= olved to its value prior to token concatentation and result in KVM effectively ge= nerating X86_FEATURE_BIT(SPEC_CTRL_SSBD_SHIFT). One of the proposed solutions is to rename all of the SPEC_CTRL_* bit defin= itions to add a MSR_ prefix, e.g. to generate MSR_SPEC_CTRL_SSBD and avoid the con= flict. My recollection from the IA32_FEATURE_CONTROL rework a few years back is th= at you wanted to prioritize shorter names over having everything namespaced with M= SR_, i.e. that this approach is a non-starter.