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AJvYcCV5hL363pRulRu4J3sYj1HpEyB3jTZ7cwswclQy6rX6gvWeV1r/M6NaKec2PPU5kaMN+ZAu2UQdMQSM5KrssDIyB5H0xJvf5zekZoKC X-Gm-Message-State: AOJu0Yy4HpuVyxExThO3DkAvuj2MEhwaMd3T8Z5zLtP+dJQhjbwlMmjf 71XwMt2hax/rfRf06QVfk/MDVqeRtgk4wGJPh5T39YjbLcGLVjVrKRLFnLsXsDFvb62m5GQSTfr acA== X-Google-Smtp-Source: AGHT+IGpZQvns4Yv1Ia7UPGh54uJfN/xbxbZf9g7hwoRt6m+NYgzW4Xj758L8HuOWnwP714lqGXrlndPbvM= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a05:6a02:f07:b0:7bd:91f4:e07c with SMTP id 41be03b00d2f7-7bd920429c2mr6356a12.0.1723036203694; Wed, 07 Aug 2024 06:10:03 -0700 (PDT) Date: Wed, 7 Aug 2024 06:10:02 -0700 In-Reply-To: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240806053701.138337-1-eiichi.tsukata@nutanix.com> Message-ID: Subject: Re: [RFC PATCH] KVM: x86: hyper-v: Inhibit APICv with VP Assist on SPR/EMR From: Sean Christopherson To: Paolo Bonzini Cc: Eiichi Tsukata , chao.gao@intel.com, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, vkuznets@redhat.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, jon@nutanix.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable On Tue, Aug 06, 2024, Paolo Bonzini wrote: > On Tue, Aug 6, 2024 at 6:03=E2=80=AFPM Sean Christopherson wrote: > > > As is noted in [1], this issue is considered to be a microcode issue > > > specific to SPR/EMR. > > > > I don't think we can claim that without a more explicit statement from = Intel. > > And I would really like Intel to clarify exactly what is going on, so t= hat (a) > > it can be properly documented and (b) we can implement a precise, targe= ted > > workaround in KVM. >=20 > It is not even clear to me why this patch has any effect at all, > because PV EOI and APICv don't work together anyway: PV EOI requires > apic->highest_isr_cache =3D=3D -1 (see apic_sync_pv_eoi_to_guest()) but > the cache is only set without APICv (see apic_set_isr()). Therefore, > PV EOI should be basically a no-op with APICv in use. Per Chao, this is a ucode bug though. Speculating wildly, I wonder if Inte= l added acceleration and/or redirection of HV_X64_MSR_EOI when APICv is enabled, e.= g. to speed up existing VMs, and something went sideways.