Re: [PATCH 0/4] Enable PMU for ArrowLake-H

Liang, Kan
2024-08-08T16:07:32Z

On 2024-08-08 10:02 a.m., Dapeng Mi wrote:
> ArrowLake-H is a specific variant of regular ArrowLake. It shares same
> PMU features on lioncove P-cores and skymont E-cores with regular
> ArrowLake except ArrowLake-H adds extra crestmont uarch E-cores.
>
> Thus ArrowLake-H contains two different atom uarchs. This is totally
> different with previous Intel hybrid platforms which contains only one
> kind of atom uarchs. In this case, it's not enough to distinguish the
> uarchs just by core type. So CPUID.1AH.EAX[23:0] provides an unique
> native model ID for each uarch, this unique native model ID combining
> the core type can be used to uniquely identity the uarch.
>
> This patch series introduces PMU support for ArrowLake-H. Besides
> inheriting the same PMU support from regular ArrowLake, it leverages
> the native model ID to detect the 2nd kind of atom uarch core and
> enables PMU support. To distinguish the two atom uarchs in sysfs, the
> PMU of 2nd atom uarch is named to "cpu_atom2".
>
> Run basic counting, PMI based sampling, PEBS based sampling, LBR and
> topdown metrics tests on ArrowLake-H platform, no issue is found.
>
> Dapeng Mi (4):
> perf/x86: Refine hybrid_pmu_type defination
> x86/cpu/intel: Define helper to get CPU core native ID
> perf/x86/intel: Support hybrid PMU with multiple atom uarchs
> perf/x86/intel: Add PMU support for ArrowLake-H

For the series,

Reviewed-by: Kan Liang <kan.liang@linux.intel.com>

Thanks,
Kan
>
> arch/x86/events/intel/core.c | 129 ++++++++++++++++++++++++++++++++---
> arch/x86/events/intel/ds.c | 21 ++++++
> arch/x86/events/perf_event.h | 33 ++++++---
> arch/x86/include/asm/cpu.h | 6 ++
> arch/x86/kernel/cpu/intel.c | 15 ++++
> 5 files changed, 186 insertions(+), 18 deletions(-)
>
>
> base-commit: 8400291e289ee6b2bf9779ff1c83a291501f017b