* [PATCH -fixes] riscv: Fix out-of-bounds when accessing Andes per hart vendor extension array
@ 2024-08-11 15:02 Alexandre Ghiti
2024-08-12 15:16 ` Conor Dooley
2024-08-14 1:29 ` Charlie Jenkins
0 siblings, 2 replies; 3+ messages in thread
From: Alexandre Ghiti @ 2024-08-11 15:02 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Andy Chiu,
Alexandre Ghiti, linux-riscv, linux-kernel
The out-of-bounds access is reported by UBSAN:
[ 0.000000] UBSAN: array-index-out-of-bounds in ../arch/riscv/kernel/vendor_extensions.c:41:66
[ 0.000000] index -1 is out of range for type 'riscv_isavendorinfo [32]'
[ 0.000000] CPU: 0 UID: 0 PID: 0 Comm: swapper Not tainted 6.11.0-rc2ubuntu-defconfig #2
[ 0.000000] Hardware name: riscv-virtio,qemu (DT)
[ 0.000000] Call Trace:
[ 0.000000] [<ffffffff94e078ba>] dump_backtrace+0x32/0x40
[ 0.000000] [<ffffffff95c83c1a>] show_stack+0x38/0x44
[ 0.000000] [<ffffffff95c94614>] dump_stack_lvl+0x70/0x9c
[ 0.000000] [<ffffffff95c94658>] dump_stack+0x18/0x20
[ 0.000000] [<ffffffff95c8bbb2>] ubsan_epilogue+0x10/0x46
[ 0.000000] [<ffffffff95485a82>] __ubsan_handle_out_of_bounds+0x94/0x9c
[ 0.000000] [<ffffffff94e09442>] __riscv_isa_vendor_extension_available+0x90/0x92
[ 0.000000] [<ffffffff94e043b6>] riscv_cpufeature_patch_func+0xc4/0x148
[ 0.000000] [<ffffffff94e035f8>] _apply_alternatives+0x42/0x50
[ 0.000000] [<ffffffff95e04196>] apply_boot_alternatives+0x3c/0x100
[ 0.000000] [<ffffffff95e05b52>] setup_arch+0x85a/0x8bc
[ 0.000000] [<ffffffff95e00ca0>] start_kernel+0xa4/0xfb6
This happens because we unconditionally use the cpu parameter to access
this array. But if -1 is passed, that means we should not and we don't
need to access this array, so simply prevent accessing the array in that case.
Fixes: 23c996fc2bc1 ("riscv: Extend cpufeature.c to detect vendor extensions")
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
---
arch/riscv/kernel/vendor_extensions.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/kernel/vendor_extensions.c b/arch/riscv/kernel/vendor_extensions.c
index b6c1e7b5d34b..01dc79b1d17b 100644
--- a/arch/riscv/kernel/vendor_extensions.c
+++ b/arch/riscv/kernel/vendor_extensions.c
@@ -27,7 +27,7 @@ const size_t riscv_isa_vendor_ext_list_size = ARRAY_SIZE(riscv_isa_vendor_ext_li
* @bit: bit position of the desired extension
* Return: true or false
*
- * NOTE: When cpu is -1, will check if extension is available on all cpus
+ * NOTE: When cpu is VENDOR_EXT_ALL_CPUS, will check if extension is available on all cpus
*/
bool __riscv_isa_vendor_extension_available(int cpu, unsigned long vendor, unsigned int bit)
{
@@ -38,14 +38,15 @@ bool __riscv_isa_vendor_extension_available(int cpu, unsigned long vendor, unsig
#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_ANDES
case ANDES_VENDOR_ID:
bmap = &riscv_isa_vendor_ext_list_andes.all_harts_isa_bitmap;
- cpu_bmap = &riscv_isa_vendor_ext_list_andes.per_hart_isa_bitmap[cpu];
+ if (cpu != VENDOR_EXT_ALL_CPUS)
+ cpu_bmap = &riscv_isa_vendor_ext_list_andes.per_hart_isa_bitmap[cpu];
break;
#endif
default:
return false;
}
- if (cpu != -1)
+ if (cpu != VENDOR_EXT_ALL_CPUS)
bmap = &cpu_bmap[cpu];
if (bit >= RISCV_ISA_VENDOR_EXT_MAX)
--
2.39.2
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH -fixes] riscv: Fix out-of-bounds when accessing Andes per hart vendor extension array
2024-08-11 15:02 [PATCH -fixes] riscv: Fix out-of-bounds when accessing Andes per hart vendor extension array Alexandre Ghiti
@ 2024-08-12 15:16 ` Conor Dooley
2024-08-14 1:29 ` Charlie Jenkins
1 sibling, 0 replies; 3+ messages in thread
From: Conor Dooley @ 2024-08-12 15:16 UTC (permalink / raw)
To: Alexandre Ghiti
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Andy Chiu, linux-riscv,
linux-kernel
[-- Attachment #1: Type: text/plain, Size: 1741 bytes --]
On Sun, Aug 11, 2024 at 05:02:29PM +0200, Alexandre Ghiti wrote:
> The out-of-bounds access is reported by UBSAN:
>
> [ 0.000000] UBSAN: array-index-out-of-bounds in ../arch/riscv/kernel/vendor_extensions.c:41:66
> [ 0.000000] index -1 is out of range for type 'riscv_isavendorinfo [32]'
> [ 0.000000] CPU: 0 UID: 0 PID: 0 Comm: swapper Not tainted 6.11.0-rc2ubuntu-defconfig #2
> [ 0.000000] Hardware name: riscv-virtio,qemu (DT)
> [ 0.000000] Call Trace:
> [ 0.000000] [<ffffffff94e078ba>] dump_backtrace+0x32/0x40
> [ 0.000000] [<ffffffff95c83c1a>] show_stack+0x38/0x44
> [ 0.000000] [<ffffffff95c94614>] dump_stack_lvl+0x70/0x9c
> [ 0.000000] [<ffffffff95c94658>] dump_stack+0x18/0x20
> [ 0.000000] [<ffffffff95c8bbb2>] ubsan_epilogue+0x10/0x46
> [ 0.000000] [<ffffffff95485a82>] __ubsan_handle_out_of_bounds+0x94/0x9c
> [ 0.000000] [<ffffffff94e09442>] __riscv_isa_vendor_extension_available+0x90/0x92
> [ 0.000000] [<ffffffff94e043b6>] riscv_cpufeature_patch_func+0xc4/0x148
> [ 0.000000] [<ffffffff94e035f8>] _apply_alternatives+0x42/0x50
> [ 0.000000] [<ffffffff95e04196>] apply_boot_alternatives+0x3c/0x100
> [ 0.000000] [<ffffffff95e05b52>] setup_arch+0x85a/0x8bc
> [ 0.000000] [<ffffffff95e00ca0>] start_kernel+0xa4/0xfb6
>
> This happens because we unconditionally use the cpu parameter to access
> this array. But if -1 is passed, that means we should not and we don't
> need to access this array, so simply prevent accessing the array in that case.
>
> Fixes: 23c996fc2bc1 ("riscv: Extend cpufeature.c to detect vendor extensions")
> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH -fixes] riscv: Fix out-of-bounds when accessing Andes per hart vendor extension array
2024-08-11 15:02 [PATCH -fixes] riscv: Fix out-of-bounds when accessing Andes per hart vendor extension array Alexandre Ghiti
2024-08-12 15:16 ` Conor Dooley
@ 2024-08-14 1:29 ` Charlie Jenkins
1 sibling, 0 replies; 3+ messages in thread
From: Charlie Jenkins @ 2024-08-14 1:29 UTC (permalink / raw)
To: Alexandre Ghiti
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Andy Chiu, linux-riscv,
linux-kernel
On Sun, Aug 11, 2024 at 05:02:29PM +0200, Alexandre Ghiti wrote:
> The out-of-bounds access is reported by UBSAN:
>
> [ 0.000000] UBSAN: array-index-out-of-bounds in ../arch/riscv/kernel/vendor_extensions.c:41:66
> [ 0.000000] index -1 is out of range for type 'riscv_isavendorinfo [32]'
> [ 0.000000] CPU: 0 UID: 0 PID: 0 Comm: swapper Not tainted 6.11.0-rc2ubuntu-defconfig #2
> [ 0.000000] Hardware name: riscv-virtio,qemu (DT)
> [ 0.000000] Call Trace:
> [ 0.000000] [<ffffffff94e078ba>] dump_backtrace+0x32/0x40
> [ 0.000000] [<ffffffff95c83c1a>] show_stack+0x38/0x44
> [ 0.000000] [<ffffffff95c94614>] dump_stack_lvl+0x70/0x9c
> [ 0.000000] [<ffffffff95c94658>] dump_stack+0x18/0x20
> [ 0.000000] [<ffffffff95c8bbb2>] ubsan_epilogue+0x10/0x46
> [ 0.000000] [<ffffffff95485a82>] __ubsan_handle_out_of_bounds+0x94/0x9c
> [ 0.000000] [<ffffffff94e09442>] __riscv_isa_vendor_extension_available+0x90/0x92
> [ 0.000000] [<ffffffff94e043b6>] riscv_cpufeature_patch_func+0xc4/0x148
> [ 0.000000] [<ffffffff94e035f8>] _apply_alternatives+0x42/0x50
> [ 0.000000] [<ffffffff95e04196>] apply_boot_alternatives+0x3c/0x100
> [ 0.000000] [<ffffffff95e05b52>] setup_arch+0x85a/0x8bc
> [ 0.000000] [<ffffffff95e00ca0>] start_kernel+0xa4/0xfb6
>
> This happens because we unconditionally use the cpu parameter to access
> this array. But if -1 is passed, that means we should not and we don't
> need to access this array, so simply prevent accessing the array in that case.
>
> Fixes: 23c996fc2bc1 ("riscv: Extend cpufeature.c to detect vendor extensions")
> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
> ---
> arch/riscv/kernel/vendor_extensions.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/arch/riscv/kernel/vendor_extensions.c b/arch/riscv/kernel/vendor_extensions.c
> index b6c1e7b5d34b..01dc79b1d17b 100644
> --- a/arch/riscv/kernel/vendor_extensions.c
> +++ b/arch/riscv/kernel/vendor_extensions.c
> @@ -27,7 +27,7 @@ const size_t riscv_isa_vendor_ext_list_size = ARRAY_SIZE(riscv_isa_vendor_ext_li
> * @bit: bit position of the desired extension
> * Return: true or false
> *
> - * NOTE: When cpu is -1, will check if extension is available on all cpus
> + * NOTE: When cpu is VENDOR_EXT_ALL_CPUS, will check if extension is available on all cpus
> */
> bool __riscv_isa_vendor_extension_available(int cpu, unsigned long vendor, unsigned int bit)
> {
> @@ -38,14 +38,15 @@ bool __riscv_isa_vendor_extension_available(int cpu, unsigned long vendor, unsig
> #ifdef CONFIG_RISCV_ISA_VENDOR_EXT_ANDES
> case ANDES_VENDOR_ID:
> bmap = &riscv_isa_vendor_ext_list_andes.all_harts_isa_bitmap;
> - cpu_bmap = &riscv_isa_vendor_ext_list_andes.per_hart_isa_bitmap[cpu];
> + if (cpu != VENDOR_EXT_ALL_CPUS)
> + cpu_bmap = &riscv_isa_vendor_ext_list_andes.per_hart_isa_bitmap[cpu];
> break;
> #endif
> default:
> return false;
> }
>
> - if (cpu != -1)
> + if (cpu != VENDOR_EXT_ALL_CPUS)
> bmap = &cpu_bmap[cpu];
>
> if (bit >= RISCV_ISA_VENDOR_EXT_MAX)
> --
> 2.39.2
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
The line that is setting the cpu_bmap shouldn't be indexing into it at
all. It is supposed to be:
cpu_bmap = &riscv_isa_vendor_ext_list_andes.per_hart_isa_bitmap;
The indexing is handled later on by the if-statement.
Thank you for looking into this.
- Charlie
^ permalink raw reply [flat|nested] 3+ messages in thread
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2024-08-11 15:02 [PATCH -fixes] riscv: Fix out-of-bounds when accessing Andes per hart vendor extension array Alexandre Ghiti
2024-08-12 15:16 ` Conor Dooley
2024-08-14 1:29 ` Charlie Jenkins
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