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[35.197.141.202]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2d613941e6esm1395309a91.26.2024.08.22.03.31.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Aug 2024 03:31:55 -0700 (PDT) Date: Thu, 22 Aug 2024 10:31:45 +0000 From: Pranjal Shrivastava To: Manivannan Sadhasivam Cc: Rob Clark , iommu@lists.linux.dev, linux-arm-msm@vger.kernel.org, Stephen Boyd , Robin Murphy , Rob Clark , Will Deacon , Joerg Roedel , Jason Gunthorpe , Jerry Snitselaar , Rob Herring , Krzysztof Kozlowski , Georgi Djakov , Dmitry Baryshkov , "moderated list:ARM SMMU DRIVERS" , open list Subject: Re: [PATCH v3 3/3] iommu/arm-smmu: Pretty-print context fault related regs Message-ID: References: <20240701162025.375134-1-robdclark@gmail.com> <20240701162025.375134-4-robdclark@gmail.com> <20240822100941.3tfqpjskzq43slfw@thinkpad> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240822100941.3tfqpjskzq43slfw@thinkpad> On Thu, Aug 22, 2024 at 03:39:41PM +0530, Manivannan Sadhasivam wrote: > On Mon, Jul 01, 2024 at 09:20:12AM -0700, Rob Clark wrote: > > From: Rob Clark > > > > Parse out the bitfields for easier-to-read fault messages. > > > > Signed-off-by: Rob Clark > > --- > > .../iommu/arm/arm-smmu/arm-smmu-qcom-debug.c | 52 +++++--------- > > drivers/iommu/arm/arm-smmu/arm-smmu.c | 70 +++++++++++++++---- > > drivers/iommu/arm/arm-smmu/arm-smmu.h | 21 ++++++ > > 3 files changed, 92 insertions(+), 51 deletions(-) > > > > [...] > > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c > > index 23cf91ac409b..79ec911ae151 100644 > > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c > > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c > > @@ -405,32 +405,72 @@ static const struct iommu_flush_ops arm_smmu_s2_tlb_ops_v1 = { > > .tlb_add_page = arm_smmu_tlb_add_page_s2_v1, > > }; > > > > + > > +void arm_smmu_read_context_fault_info(struct arm_smmu_device *smmu, int idx, > > + struct arm_smmu_context_fault_info *cfi) > > +{ > > + cfi->iova = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_FAR); > > + cfi->fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR); > > + cfi->fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0); > > + cfi->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx)); > > +} > > + > > +void arm_smmu_print_context_fault_info(struct arm_smmu_device *smmu, int idx, > > + const struct arm_smmu_context_fault_info *cfi) > > +{ > > + dev_dbg(smmu->dev, > > + "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n", > > + cfi->fsr, cfi->iova, cfi->fsynr, cfi->cbfrsynra, idx); > > + > > I just happen to hit an IOMMU fault in 6.11-rc4 and I did not see the 'Unhandled > context fault' log, but just the register dump in dmesg. Tracking that lead me > to this patch. > > May I know the reasoning behind making the actual error message _dbg()? It is > intentional first place? > > - Mani Hi Mani, That was a miss in this series, but it was fixed recently in [1]. I think it should land soon. [1] https://lore.kernel.org/linux-iommu/172381862229.1794487.17068761066364130246.b4-ty@kernel.org/ Thanks, Pranjal > > > + dev_err(smmu->dev, "FSR = %08x [%s%sFormat=%u%s%s%s%s%s%s%s%s], SID=0x%x\n", > > + cfi->fsr, > > + (cfi->fsr & ARM_SMMU_CB_FSR_MULTI) ? "MULTI " : "", > > + (cfi->fsr & ARM_SMMU_CB_FSR_SS) ? "SS " : "", > > + (u32)FIELD_GET(ARM_SMMU_CB_FSR_FORMAT, cfi->fsr), > > + (cfi->fsr & ARM_SMMU_CB_FSR_UUT) ? " UUT" : "", > > + (cfi->fsr & ARM_SMMU_CB_FSR_ASF) ? " ASF" : "", > > + (cfi->fsr & ARM_SMMU_CB_FSR_TLBLKF) ? " TLBLKF" : "", > > + (cfi->fsr & ARM_SMMU_CB_FSR_TLBMCF) ? " TLBMCF" : "", > > + (cfi->fsr & ARM_SMMU_CB_FSR_EF) ? " EF" : "", > > + (cfi->fsr & ARM_SMMU_CB_FSR_PF) ? " PF" : "", > > + (cfi->fsr & ARM_SMMU_CB_FSR_AFF) ? " AFF" : "", > > + (cfi->fsr & ARM_SMMU_CB_FSR_TF) ? " TF" : "", > > + cfi->cbfrsynra); > > + > > + dev_err(smmu->dev, "FSYNR0 = %08x [S1CBNDX=%u%s%s%s%s%s%s PLVL=%u]\n", > > + cfi->fsynr, > > + (u32)FIELD_GET(ARM_SMMU_CB_FSYNR0_S1CBNDX, cfi->fsynr), > > + (cfi->fsynr & ARM_SMMU_CB_FSYNR0_AFR) ? " AFR" : "", > > + (cfi->fsynr & ARM_SMMU_CB_FSYNR0_PTWF) ? " PTWF" : "", > > + (cfi->fsynr & ARM_SMMU_CB_FSYNR0_NSATTR) ? " NSATTR" : "", > > + (cfi->fsynr & ARM_SMMU_CB_FSYNR0_IND) ? " IND" : "", > > + (cfi->fsynr & ARM_SMMU_CB_FSYNR0_PNU) ? " PNU" : "", > > + (cfi->fsynr & ARM_SMMU_CB_FSYNR0_WNR) ? " WNR" : "", > > + (u32)FIELD_GET(ARM_SMMU_CB_FSYNR0_PLVL, cfi->fsynr)); > > +} > > + > > static irqreturn_t arm_smmu_context_fault(int irq, void *dev) > > { > > - u32 fsr, fsynr, cbfrsynra; > > - unsigned long iova; > > + struct arm_smmu_context_fault_info cfi; > > struct arm_smmu_domain *smmu_domain = dev; > > struct arm_smmu_device *smmu = smmu_domain->smmu; > > + static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL, > > + DEFAULT_RATELIMIT_BURST); > > int idx = smmu_domain->cfg.cbndx; > > int ret; > > > > - fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR); > > - if (!(fsr & ARM_SMMU_CB_FSR_FAULT)) > > - return IRQ_NONE; > > + arm_smmu_read_context_fault_info(smmu, idx, &cfi); > > > > - fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0); > > - iova = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_FAR); > > - cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx)); > > + if (!(cfi.fsr & ARM_SMMU_CB_FSR_FAULT)) > > + return IRQ_NONE; > > > > - ret = report_iommu_fault(&smmu_domain->domain, NULL, iova, > > - fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ); > > + ret = report_iommu_fault(&smmu_domain->domain, NULL, cfi.iova, > > + cfi.fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ); > > > > - if (ret == -ENOSYS) > > - dev_err_ratelimited(smmu->dev, > > - "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n", > > - fsr, iova, fsynr, cbfrsynra, idx); > > + if (ret == -ENOSYS && __ratelimit(&rs)) > > + arm_smmu_print_context_fault_info(smmu, idx, &cfi); > > > > - arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr); > > + arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, cfi.fsr); > > return IRQ_HANDLED; > > } > > > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h > > index b04a00126a12..e2aeb511ae90 100644 > > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h > > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h > > @@ -198,6 +198,7 @@ enum arm_smmu_cbar_type { > > #define ARM_SMMU_CB_FSR 0x58 > > #define ARM_SMMU_CB_FSR_MULTI BIT(31) > > #define ARM_SMMU_CB_FSR_SS BIT(30) > > +#define ARM_SMMU_CB_FSR_FORMAT GENMASK(10, 9) > > #define ARM_SMMU_CB_FSR_UUT BIT(8) > > #define ARM_SMMU_CB_FSR_ASF BIT(7) > > #define ARM_SMMU_CB_FSR_TLBLKF BIT(6) > > @@ -223,7 +224,14 @@ enum arm_smmu_cbar_type { > > #define ARM_SMMU_CB_FAR 0x60 > > > > #define ARM_SMMU_CB_FSYNR0 0x68 > > +#define ARM_SMMU_CB_FSYNR0_PLVL GENMASK(1, 0) > > #define ARM_SMMU_CB_FSYNR0_WNR BIT(4) > > +#define ARM_SMMU_CB_FSYNR0_PNU BIT(5) > > +#define ARM_SMMU_CB_FSYNR0_IND BIT(6) > > +#define ARM_SMMU_CB_FSYNR0_NSATTR BIT(8) > > +#define ARM_SMMU_CB_FSYNR0_PTWF BIT(10) > > +#define ARM_SMMU_CB_FSYNR0_AFR BIT(11) > > +#define ARM_SMMU_CB_FSYNR0_S1CBNDX GENMASK(23, 16) > > > > #define ARM_SMMU_CB_FSYNR1 0x6c > > > > @@ -533,4 +541,17 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu); > > void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx); > > int arm_mmu500_reset(struct arm_smmu_device *smmu); > > > > +struct arm_smmu_context_fault_info { > > + unsigned long iova; > > + u32 fsr; > > + u32 fsynr; > > + u32 cbfrsynra; > > +}; > > + > > +void arm_smmu_read_context_fault_info(struct arm_smmu_device *smmu, int idx, > > + struct arm_smmu_context_fault_info *cfi); > > + > > +void arm_smmu_print_context_fault_info(struct arm_smmu_device *smmu, int idx, > > + const struct arm_smmu_context_fault_info *cfi); > > + > > #endif /* _ARM_SMMU_H */ > > -- > > 2.45.2 > > > > > > -- > மணிவண்ணன் சதாசிவம்