Re: [PATCH 1/2] ARM: dts: imx6ul-geam: fix fsl,pins property in tscgrp pinctrl

Michael Nazzareno Trimarchi
2024-08-31T10:16:10Z

HI

On Sat, Aug 31, 2024 at 12:11 PM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> The property is "fsl,pins", not "fsl,pin". Wrong property means the pin
> configuration was not applied. Fixes dtbs_check warnings:
>
> imx6ul-geam.dtb: pinctrl@20e0000: tscgrp: 'fsl,pins' is a required property
> imx6ul-geam.dtb: pinctrl@20e0000: tscgrp: 'fsl,pin' does not match any of the regexes: 'pinctrl-[0-9]+'
>
> Cc: <stable@vger.kernel.org>
> Fixes: a58e4e608bc8 ("ARM: dts: imx6ul-geam: Add Engicam IMX6UL GEA M6UL initial support")
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts
> index cdbb8c435cd6..601d89b904cd 100644
> --- a/arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts
> +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts
> @@ -365,7 +365,7 @@ MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0
> };
>
> pinctrl_tsc: tscgrp {
> - fsl,pin = <
> + fsl,pins = <
> MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
> MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
> MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
> --
> 2.43.0
>

Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>

Thank you
Michael