Re: [PATCH v2 00/19] iommufd: Add VIOMMU infrastructure (Part-1)

Nicolin Chen
2024-09-30T22:00:08Z

On Sun, Sep 29, 2024 at 03:16:55PM +0800, Yi Liu wrote:
> > > > I feel these two might act somehow similarly to the two DIDs
> > > > during nested translations?
> > >
> > > not quite the same. Is it possible that the ASID is the same for stage-1?
> > > Intel VT-d side can have the pasid to be the same. Like the gIOVA, all
> > > devices use the same ridpasid. Like the scenario I replied to Baolu[1],
> > > do er choose to use different DIDs to differentiate the caches for the
> > > two devices.
> >
> > On ARM, each S1 domain (either a normal stage-1 PASID=0 domain or
> > an SVA PASID>0 domain) has a unique ASID.
>
> I see. Looks like ASID is not the PASID.

It's not. PASID is called Substream ID in SMMU term. It's used to
index the PASID table. For cache invalidations, a PASID (ssid) is
for ATC (dev cache) or PASID table entry invalidation only.

> > So it unlikely has the
> > situation of two identical ASIDs if they are on the same vIOMMU,
> > because the ASID pool is per IOMMU instance (whether p or v).
> >
> > With two vIOMMU instances, there might be the same ASIDs but they
> > will be tagged with different VMIDs.
> >
> > > [1]
> > > https://lore.kernel.org/linux-iommu/4bc9bd20-5aae-440d-84fd-f530d0747c23@intel.com/
> >
> > Is "gIOVA" a type of invalidation that only uses "address" out of
> > "PASID, DID and address"? I.e. PASID and DID are not provided via
> > the invalidation request, so it's going to broadcast all viommus?
>
> gIOVA is just a term v.s. vSVA. Just want to differentiate it from vSVA. :)
> PASID and DID are still provided in the invalidation.

I am still not getting this gIOVA. What it does exactly v.s. vSVA?
And should RIDPASID be IOMMU_NO_PASID?

Nicolin