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Wed, 11 Sep 2024 13:53:16 -0700 Date: Wed, 11 Sep 2024 13:53:16 -0700 From: Nicolin Chen To: "Tian, Kevin" CC: Jason Gunthorpe , "will@kernel.org" , "joro@8bytes.org" , "suravee.suthikulpanit@amd.com" , "robin.murphy@arm.com" , "dwmw2@infradead.org" , "baolu.lu@linux.intel.com" , "shuah@kernel.org" , "linux-kernel@vger.kernel.org" , "iommu@lists.linux.dev" , "linux-arm-kernel@lists.infradead.org" , "linux-kselftest@vger.kernel.org" , "eric.auger@redhat.com" , "jean-philippe@linaro.org" , "mdf@kernel.org" , "mshavit@google.com" , "shameerali.kolothum.thodi@huawei.com" , "smostafa@google.com" , "Liu, Yi L" Subject: Re: [PATCH v2 17/19] iommu/arm-smmu-v3: Add arm_smmu_viommu_cache_invalidate Message-ID: References: <4b61aba3bc6c1cce628d9db44d5b18ea567a8be1.1724776335.git.nicolinc@nvidia.com> <20240905162039.GT1358970@nvidia.com> <20240905182148.GA1358970@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Sep 2024 20:53:42.2582 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 250959df-9181-47a2-bd65-08dcd2a3d1e7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF00000205.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7038 On Wed, Sep 11, 2024 at 08:13:01AM +0000, Tian, Kevin wrote: > > > > Yes, many more patches, and don't try to do it now.. But we can copy > > > > the vmid from the s2 and place it in the viommu struct during > > > > allocation time. > > > > > > > > > > does it assume that a viommu object cannot span multiple physical > > > IOMMUs so there is only one vmid per viommu? > > > > I think so. One the reasons of introducing vIOMMU is to maintain > > the shareability across physical IOMMUs at the s2 HWPT_PAGING. > > > > I don't quite get it. e.g. for intel-iommu the S2 domain itself can > be shared across physical IOMMUs SMMU does the same, but needs a VMID per pSMMU to tag that S2 domain: vIOMMU0 (VMIDx of pSMMU0) -> shared S2 vIOMMU1 (VMIDy of pSMMU1) -> shared S2 Note: x and y might be different. > then what is the problem > preventing a vIOMMU object using that S2 to span multiple IOMMUs? Jason previously suggested the way of implementing multi-vIOMMU in a VMM to be one vIOMMU object representing a vIOMMU instance (of a physical IOMMU) in the VM. So, it'd be only one VMID per one vIOMMU object. Sharing one vIOMMU object on the other hand needs the vIOMMU to hold a list of VMIDs for all (or attached?) physical IOMMUs. This would change what a vIOMMU object represents. > Probably there is a good reason e.g. for simplification or better > aligned with hw accel stuff. But it's not explained clearly so far. I will try emphasizing that in the next version, likely in the rst file that I am patching for HWPT_PAGING/NESTED at this point. Thanks Nicolin