From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2172EDF60; Fri, 13 Sep 2024 15:24:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726241073; cv=none; b=oHmu/b65PMfNy93WSTqL6o1AFubaCpu+uYV4f9G/wUXgrH67SD+5P6/X7alvfll+c4NjFv49Qfbxz5pW1b3spZJxCtSGbHNLKchZ9eL3ySSQ4gLtzWGtay2KJVx7vnRryeQwtyErew44POkCbJxmNx1AGqrpoVdESk5jRV+FGw4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726241073; c=relaxed/simple; bh=xlpLRV9hViJBcrtkalP94EioikNI5rImcEjIIh9vJeY=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=kepuyt7fZ7UVKz+cC0jB6X6+2pXmiG2+W9I/L+cMSsiqO0r8/SPiw0rM8GUBMRDFDRDTpBlmguf5/B99gFeVw8daoAkJ9l/VOFqEihbZS11kvaohPvi+zxEdCZn+LDNUPHQe0rQXMVKggtNDewLIx/ILrgS/kRrkc/84J07UM+I= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=i10wbSEX; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="i10wbSEX" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CCF77C4CEC0; Fri, 13 Sep 2024 15:24:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1726241072; bh=xlpLRV9hViJBcrtkalP94EioikNI5rImcEjIIh9vJeY=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=i10wbSEXjicEZUx5Q3t5Ko31o/Rmll4l/df1dDvTnAuLmCzz1wPpYXc3xBV0n+b+Q o8JFVG+3OqAoXPG98QGh5K6y9mYYLIKNF70r9PPQTCT9NuXge1HsFkxJmkyVG7+kx4 e3K/eS7MCvCIwBTePFYz7RPka4apRYx9aRtyVarQJr2sg+013QPwJvR8pCL0PnB0QQ nQb1L2KNZPOlCNDhCWbQ9QLmmhW2R+zznvLHh45MPtjNy8JhmLJNqETNOPX7PVaJwq FoMYYVTFOPJ4KNWsREtZcg9T4cfmuHp0CkUXXBtxtfHFvW/RKH+EQIavr68RkEiEnK Ydq59DcQXmh3g== Date: Fri, 13 Sep 2024 09:24:29 -0600 From: Keith Busch To: Manivannan Sadhasivam Cc: Kai-Heng Feng , Nirmal Patel , jonathan.derrick@linux.dev, acelan.kao@canonical.com, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kaihengfeng@gmail.com Subject: Re: [PATCH] PCI: vmd: Delay interrupt handling on MTL VMD controller Message-ID: References: <20240903025544.286223-1-kai.heng.feng@canonical.com> <20240903042852.v7ootuenihi5wjpn@thinkpad> <20240904062219.x7kft2l3gq4qsojc@thinkpad> <20240912104547.00005865@linux.intel.com> <20240913111142.4cgrmirofhhgrbqm@thinkpad> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240913111142.4cgrmirofhhgrbqm@thinkpad> On Fri, Sep 13, 2024 at 04:41:42PM +0530, Manivannan Sadhasivam wrote: > I'm not able to understand the bug properly. The erratum indicates that the MSI > from device reaches the VMD before other writes to the registers. So this is an > ordering issue as MSI takes precedence over other writes from the device. > > So the workaround is to read the device register in the MSI handler to make sure > the previous writes from the device are flushed. IIUC, once the MSI reaches the > VMD, it will trigger the IRQ handler in the NVMe driver and in the handler, CQE > status register is read first up. This flow matches with the workaround > suggested. > > Is any write being performed to the NVMe device before reading any register in > the MSI handler? Or the current CQE read is not able to satisfy the workaround? > Please clarify. The CQE is not a device register. It exists in host memory, so reading that from the driver isn't going to flush writes from IO devices.