From: Keith Busch <kbusch@kernel.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Kai-Heng Feng <kai.heng.feng@canonical.com>,
Nirmal Patel <nirmal.patel@linux.intel.com>,
jonathan.derrick@linux.dev, acelan.kao@canonical.com,
lpieralisi@kernel.org, kw@linux.com, robh@kernel.org,
bhelgaas@google.com, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, kaihengfeng@gmail.com
Subject: Re: [PATCH] PCI: vmd: Delay interrupt handling on MTL VMD controller
Date: Fri, 13 Sep 2024 10:34:46 -0600 [thread overview]
Message-ID: <ZuRppgocLShsfafm@kbusch-mbp> (raw)
In-Reply-To: <20240913161447.7irp2p5a2sjpobf3@thinkpad>
On Fri, Sep 13, 2024 at 09:44:47PM +0530, Manivannan Sadhasivam wrote:
>
> For the workaround, does it make sense to have a platform specific quirk in the
> NVMe driver? Because, reading the NVMe device register from VMD driver doesn't
> look plausible to me.
I don't know.
Does the breakage really need a register read on the device that
dispatched the original MSI? The VMD driver has no idea which device
sent it. If you really need to query every single device in the domain,
your performance is going to tank. It's bad enough issuing just a single
read in the IRQ handler, but to all of them?
next prev parent reply other threads:[~2024-09-13 16:34 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-03 2:55 [PATCH] PCI: vmd: Delay interrupt handling on MTL VMD controller Kai-Heng Feng
2024-09-03 4:28 ` Manivannan Sadhasivam
2024-09-03 7:07 ` Kai-Heng Feng
2024-09-03 8:00 ` Manivannan Sadhasivam
2024-09-03 14:51 ` Keith Busch
2024-09-04 1:57 ` Kai-Heng Feng
2024-09-04 6:22 ` Manivannan Sadhasivam
2024-09-06 1:56 ` Kai-Heng Feng
2024-09-12 17:45 ` Nirmal Patel
2024-09-13 5:55 ` Kai-Heng Feng
2024-09-13 11:11 ` Manivannan Sadhasivam
2024-09-13 15:24 ` Keith Busch
2024-09-13 16:14 ` Manivannan Sadhasivam
2024-09-13 16:34 ` Keith Busch [this message]
2024-09-03 15:29 ` Nirmal Patel
2024-09-03 16:17 ` kernel test robot
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