From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-yb1-f201.google.com (mail-yb1-f201.google.com [209.85.219.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 81F1A15747D for ; Fri, 4 Oct 2024 13:35:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.219.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728048933; cv=none; b=Lon8kQNJlrNEaYXeUvMIUKR3xf7xdlWNNBf4ByeijhEMG04JD5GPRYRHJU8QhIweJQWdTGsceKmHHk+v7S0ceybIlAdHJ5hCUORlWiYDfidG53bHW5BA1ybZHM1DTJV//JE1NAiuFivASCF9SAtyditpYmUcg1BkJ8o3V1wfmcQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728048933; c=relaxed/simple; bh=ZkmyxQ3QOTQso2mGTJ7hRHIUqp7vFnEruN8aoDO2Jok=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=QOPqdgziXgr1Qdrb5ftg0sjjNTa6eWArDoUpAmupnqIPGrC6qQRvpFK+yqQFBDIZx7bT5Yewq6JDnfUoL+U2WJszVRJ4QvGCoRM3dgeIVfAY0CNX9y0uF9YjlFaAdAzq+M+W5LhRK2IVDS8XbhqvYC0KLcsFyeqYJ2tdgB8Qaro= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=nQZyQRxZ; arc=none smtp.client-ip=209.85.219.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="nQZyQRxZ" Received: by mail-yb1-f201.google.com with SMTP id 3f1490d57ef6-e25cae769abso2880505276.0 for ; Fri, 04 Oct 2024 06:35:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1728048930; x=1728653730; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=iRKRcRUT8iLe/fkq4dl/vkLTjdTfTheBiakbS3Xtaxg=; b=nQZyQRxZ3Gwr5xPE4/CkHe/lVN1U9IMNaO1D7fMmUM6rqVi4ryEwcqaScLovw+SK78 SV6njv7uAT/XO1sRhVO5FBsDKi6ewQyBgyXAvvux94UQnGpcBX3aEI64jFlqGtHzZM7F aVsL2IMViUnztx4Y3uobrARcx+dZc4c7zeSevTJSXvbZkxWXcJjjNgmKt0lqJku+0Haf H8iBbV1U5t1auqvuB0rAj1RXDt9ZXxO0XEWsLB+czn2LY3ZdhMidkej30HAuu11k2BnA +JWgKM/PtDm37AQqPwA9mTHuXZ5sAcLbb+nyfpoAIKOmXl9z9xJw/uFTSFeZZcFNzkTD VZ1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728048930; x=1728653730; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=iRKRcRUT8iLe/fkq4dl/vkLTjdTfTheBiakbS3Xtaxg=; b=fdkBwKW3Cda4Ndw8lFnGr6u5bD4/GaAgPWXCj/c99P5IhSoQ6EZ+r8TC8xwjQkIQYp Nw9OeuTf6ybkXku83b1n+uJoEz8pn5HFFZj1ze2q+AkcvcB8bZa3Jb4AUblOskLfUkuQ 7By/O2KWwtT4Uu6DFJCVxuKx0Et7IOflafjkJwOiRaOw1Ai0Xf7LnNx+S5A5smcsixb/ Xyw7QeFmb0DqkU0biho43M8F1nzuL4udesjL2VpSH+S4XgwS6PohYsas9vBSqsNHMLVu sQ3pA6RBWY4qANzfvgQu/JmxpwRqDpYF1zb60Y0nZy9QgKnfhlzaGETgGZvwl7Co1dta a8nA== X-Forwarded-Encrypted: i=1; AJvYcCWA+BI4Q6DfFHRt2zi5abgdzyrs1D3RHWUQ4gM2ttruC/9RrnLhPB4bBuZnxddEzpiQYkqSycA5AdHDjIw=@vger.kernel.org X-Gm-Message-State: AOJu0YzCpJbl6UgyRzQFwS+SU8BiXhfj3c9nIQo3PcEGb41jHoKTA4gq qASZwGmJyCgskwwpaylpJfw7BHQM8oOy/9MArrVAI7E+KX0eVACD62khTuHu3hhhmBjXgcjGnDT OqA== X-Google-Smtp-Source: AGHT+IGrQhmBThdQjeJmJqP3+NLqTBL86x6LnHPI+mDohnEHno+IVTKZ8ehf4O7OsYSKHm7wAkLZux85E7s= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a25:d804:0:b0:e28:8f00:896a with SMTP id 3f1490d57ef6-e289393a895mr1609276.8.1728048930376; Fri, 04 Oct 2024 06:35:30 -0700 (PDT) Date: Fri, 4 Oct 2024 06:35:29 -0700 In-Reply-To: <87v7y8i6m3.fsf@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241003234337.273364-1-seanjc@google.com> <20241003234337.273364-6-seanjc@google.com> <87v7y8i6m3.fsf@redhat.com> Message-ID: Subject: Re: [PATCH 05/11] KVM: selftests: Configure XCR0 to max supported value by default From: Sean Christopherson To: Vitaly Kuznetsov Cc: Paolo Bonzini , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="us-ascii" On Fri, Oct 04, 2024, Vitaly Kuznetsov wrote: > Sean Christopherson writes: > > > To play nice with compilers generating AVX instructions, set CR4.OSXSAVE > > and configure XCR0 by default when creating selftests vCPUs. Some distros > > have switched gcc to '-march=x86-64-v3' by default, and while it's hard to > > find a CPU which doesn't support AVX today, many KVM selftests fail with > > > > ==== Test Assertion Failure ==== > > lib/x86_64/processor.c:570: Unhandled exception in guest > > pid=72747 tid=72747 errno=4 - Interrupted system call > > Unhandled exception '0x6' at guest RIP '0x4104f7' > > > > due to selftests not enabling AVX by default for the guest. The failure > > is easy to reproduce elsewhere with: > > > > $ make clean && CFLAGS='-march=x86-64-v3' make -j && ./x86_64/kvm_pv_test > > > > E.g. gcc-13 with -march=x86-64-v3 compiles this chunk from selftests' > > kvm_fixup_exception(): > > > > regs->rip = regs->r11; > > regs->r9 = regs->vector; > > regs->r10 = regs->error_code; > > > > into this monstronsity (which is clever, but oof): > > > > 405313: c4 e1 f9 6e c8 vmovq %rax,%xmm1 > > 405318: 48 89 68 08 mov %rbp,0x8(%rax) > > 40531c: 48 89 e8 mov %rbp,%rax > > 40531f: c4 c3 f1 22 c4 01 vpinsrq $0x1,%r12,%xmm1,%xmm0 > > 405325: 49 89 6d 38 mov %rbp,0x38(%r13) > > 405329: c5 fa 7f 45 00 vmovdqu %xmm0,0x0(%rbp) > > > > Alternatively, KVM selftests could explicitly restrict the compiler to > > -march=x86-64-v2, but odds are very good that punting on AVX enabling will > > simply result in tests that "need" AVX doing their own thing, e.g. there > > are already three or so additional cleanups that can be done on top. > > Ideally, we may still want to precisely pin the set of instructions > which are used to generete guest code in selftests as the environment > where this code runs is defined by us and it may not match the host. I > can easily imaging future CPU features leading to similar issues in case > they require explicit enablement. Maybe. I suspect the cross-section of features that require explicit enablement *and* will be generated by the compiler for "regular" code will be limited to AVX and the like. E.g. the only new in -v4 is AVX512. > To achive this, we can probably separate guest code from each test into its > own compilation unit. Hopefully we don't need to worry about that for years and years :-)