From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 76350192584 for ; Mon, 30 Sep 2024 17:10:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.176 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727716218; cv=none; b=tHeR7zP2v8IbyzHUnAqDwwf5GYmczmj9U2s4XC1FCvMSZ+uslXrtZ8nz1mAA7PaHDVmuncSNfaTFIL74WaOv1Zf1UwZfd/c7yjZalXfNcSDkjKVsOZhIPH/pegVCL9mmgEAk7N6hV4KqjL4r6RLY9rXTm3sOP5xbdQ8J8nGD8tA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727716218; c=relaxed/simple; bh=DYY3gi/yxQqi/2eYpYQoIg+BIxy/g46w7yv+BZUnrdY=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=PVmlEJSFVN9hfq2OT3fb+GjPVqo5z3js+daNvJp+I8npWrUCzW776kEA2Bm+mTgWieaI3p8XcZJrDH6Y65RWCqejSRrpGWXYngC7hlJA03bRdvlhdZZ79sDfu9/oUytSQ1L81W+kXEA+nnDvxZk4ypYwDpcRSF9PLX0HiX1emsw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=hYtK6Zi+; arc=none smtp.client-ip=209.85.214.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="hYtK6Zi+" Received: by mail-pl1-f176.google.com with SMTP id d9443c01a7336-20ba8d92af9so1998545ad.3 for ; Mon, 30 Sep 2024 10:10:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1727716216; x=1728321016; darn=vger.kernel.org; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=Kx5xY759dyUvA9Oa0etxE9VI1UhfQHqL7wndkbURsJU=; b=hYtK6Zi+rvPg/Ao4wsqvxqDb/4DykqoGyCW65rFNjhxAF9hiDEwMO/Lq/I9A3l03dL 8YqteNUNdUFnHSX5qSw1HQWkvLg5/9snJZMnppD6SDT4VJFG9mq5Dyj4SvTB7otL4k2N QY8nli4pxaeMLpQKElf0ZF2KFJImCgy0R0dqKvqLBdLVTQTbp+UILqJ/p9yR8mmFNd+6 63McIgMJ1/4PWpg/91TFYs0SUMPv1hFCgVaW03U6h3bJZrE2GhCOno0NBC91Q55zQ+Ug TMKKHBsGS7nAwpQDZISa53TFj4VvOext46g+f8FfSmf5qCvb1uvsCl/oMOqCR3UDtSQk q87A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727716216; x=1728321016; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=Kx5xY759dyUvA9Oa0etxE9VI1UhfQHqL7wndkbURsJU=; b=nNqO50pgfwckhCquCi1TP9FiMU0Z8vl1xLz86fJ6Yr1UYte0DR1vwda2sV0uqfnE6O m1MnK47OCwAjqtRI+vN3YwYUpcnscboDgjsHipeaQEIeReHK7sGyDWzr3QRuZC8ZnMFf TVEnIiqNaofnCoN+8bUYo+W+iAf0X6qzU4hMoL0xtWcHcK0lrtgk8Bx5Q8w1hIpS85oR nsmUeNXz97/pKv0JSUijDbmpF/TYvDdIwqH2OsVaCjso9JUd4hxdg/7iXGQXA1KKZSOa DlTIbXyjZNxxkSz0rt6ZqFjUqk1VB9uvyP1KQyXTuof0Ny30RyGREIGP0u4pP2QhKUPf 1mTg== X-Forwarded-Encrypted: i=1; AJvYcCX+CnF7Kc1iLNleTFbpoBQjzchxI3SBPhVPzqxqyej47gbwEANg7nMVWG4ONWO1TDsdDI1M4zCb8ZAR9Z4=@vger.kernel.org X-Gm-Message-State: AOJu0YwF4FOr5oY04dKGp13EGQLAoqhdmwt+uJQqZrHgxsHEo3o1QtB9 zLNhqF/QxkaRkwaZvZfFY1mSTpSKkHXvyBP2R4Fky0i+u2dsDeKvxOupJY0eGuI= X-Google-Smtp-Source: AGHT+IHhm9pcVh5+FAyHVsQ1m3+mrrvYcuAeUKlMpqmlUG23x4p++fjWVQHljqdw9xU30Zn1dsMTzg== X-Received: by 2002:a17:903:40d1:b0:20b:3f70:2e05 with SMTP id d9443c01a7336-20b3f702f68mr178426175ad.41.1727716215778; Mon, 30 Sep 2024 10:10:15 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20b533fa125sm42501775ad.141.2024.09.30.10.10.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Sep 2024 10:10:15 -0700 (PDT) Date: Mon, 30 Sep 2024 10:10:13 -0700 From: Deepak Gupta To: Max Hsu Cc: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Atish Patra , Palmer Dabbelt , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Samuel Holland Subject: Re: [PATCH RFC v2 2/3] riscv: Add Svukte extension support Message-ID: References: <20240927-dev-maxh-svukte-rebase-2-v2-0-9afe57c33aee@sifive.com> <20240927-dev-maxh-svukte-rebase-2-v2-2-9afe57c33aee@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Disposition: inline In-Reply-To: <20240927-dev-maxh-svukte-rebase-2-v2-2-9afe57c33aee@sifive.com> On Fri, Sep 27, 2024 at 09:41:44PM +0800, Max Hsu wrote: >Svukte extension introduce senvcfg.UKTE, hstatus.HUKTE. > >This patch add CSR bit definition, and detects if Svukte ISA extension >is available, cpufeature will set the correspond bit field so the >svukte-qualified memory accesses are protected in a manner that is >timing-independent of the faulting virtual address. > >Since hstatus.HU is not enabled by linux, enabling hstatus.HUKTE will >not be affective. > >This patch depends on patch "riscv: Per-thread envcfg CSR support" [1] > >Link: https://lore.kernel.org/linux-riscv/20240814081126.956287-1-samuel.holland@sifive.com/ [1] > >Reviewed-by: Samuel Holland >Signed-off-by: Max Hsu >--- > arch/riscv/include/asm/csr.h | 2 ++ > arch/riscv/include/asm/hwcap.h | 1 + > arch/riscv/kernel/cpufeature.c | 4 ++++ > 3 files changed, 7 insertions(+) > >diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h >index 25966995da04e090ff22a11e35be9bc24712f1a8..62b50667d539c50a0bfdadd1c6ab06cda948f6a8 100644 >--- a/arch/riscv/include/asm/csr.h >+++ b/arch/riscv/include/asm/csr.h >@@ -122,6 +122,7 @@ > #define HSTATUS_VSXL _AC(0x300000000, UL) > #define HSTATUS_VSXL_SHIFT 32 > #endif >+#define HSTATUS_HUKTE _AC(0x01000000, UL) > #define HSTATUS_VTSR _AC(0x00400000, UL) > #define HSTATUS_VTW _AC(0x00200000, UL) > #define HSTATUS_VTVM _AC(0x00100000, UL) >@@ -195,6 +196,7 @@ > /* xENVCFG flags */ > #define ENVCFG_STCE (_AC(1, ULL) << 63) > #define ENVCFG_PBMTE (_AC(1, ULL) << 62) >+#define ENVCFG_UKTE (_AC(1, UL) << 8) > #define ENVCFG_CBZE (_AC(1, UL) << 7) > #define ENVCFG_CBCFE (_AC(1, UL) << 6) > #define ENVCFG_CBIE_SHIFT 4 >diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h >index 46d9de54179ed40aa7b1ea0ec011fd6eea7218df..3591a4f40131ff5958c07857a1bd1624723d6550 100644 >--- a/arch/riscv/include/asm/hwcap.h >+++ b/arch/riscv/include/asm/hwcap.h >@@ -93,6 +93,7 @@ > #define RISCV_ISA_EXT_ZCMOP 84 > #define RISCV_ISA_EXT_ZAWRS 85 > #define RISCV_ISA_EXT_SVVPTC 86 >+#define RISCV_ISA_EXT_SVUKTE 87 > > #define RISCV_ISA_EXT_XLINUXENVCFG 127 > >diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c >index 3a8eeaa9310c32fce2141aff534dc4432b32abbe..e0853cae1dc0ba844d5969a42c30d44287e3250a 100644 >--- a/arch/riscv/kernel/cpufeature.c >+++ b/arch/riscv/kernel/cpufeature.c >@@ -381,6 +381,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), > __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), > __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), >+ __RISCV_ISA_EXT_SUPERSET(svukte, RISCV_ISA_EXT_SVUKTE, riscv_xlinuxenvcfg_exts), > __RISCV_ISA_EXT_DATA(svvptc, RISCV_ISA_EXT_SVVPTC), > }; > >@@ -921,6 +922,9 @@ void riscv_user_isa_enable(void) > { > if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICBOZ)) > csr_set(CSR_ENVCFG, ENVCFG_CBZE); >+ >+ if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SVUKTE)) >+ current->thread.envcfg |= ENVCFG_UKTE; Pending merge of samuel's patches, this looks good to me. Reviewed-by: Deepak Gupta > } > > #ifdef CONFIG_RISCV_ALTERNATIVE > >-- >2.43.2 > >