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Shenoy" , Perry Yuan , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-pm@vger.kernel.org, platform-driver-x86@vger.kernel.org, Shyam Sundar S K Subject: Re: [PATCH v2 01/13] Documentation: x86: Add AMD Hardware Feedback Interface documentation Message-ID: References: <20241010193705.10362-1-mario.limonciello@amd.com> <20241010193705.10362-2-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="ScYld6gsAtJ/5B+U" Content-Disposition: inline In-Reply-To: <20241010193705.10362-2-mario.limonciello@amd.com> --ScYld6gsAtJ/5B+U Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Oct 10, 2024 at 02:36:53PM -0500, Mario Limonciello wrote: > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > +Hardware Feedback Interface For Hetero Core Scheduling On AMD Platform > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > + > +:Copyright (C) 2024 Advanced Micro Devices, Inc. All Rights Reserved. > + > +:Author: Perry Yuan Don't forget to correct the copyright reST field: diff --git a/Documentation/arch/x86/amd-hfi.rst b/Documentation/arch/x86/am= d-hfi.rst index 5ada5c5b79f4b5..82811be984799d 100644 --- a/Documentation/arch/x86/amd-hfi.rst +++ b/Documentation/arch/x86/amd-hfi.rst @@ -4,7 +4,7 @@ Hardware Feedback Interface For Hetero Core Scheduling On AMD Platform =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 -:Copyright (C) 2024 Advanced Micro Devices, Inc. All Rights Reserved. +:Copyright: 2024 Advanced Micro Devices, Inc. All Rights Reserved. =20 :Author: Perry Yuan =20 > + > +Overview > +-------- > + > +AMD Heterogeneous Core implementations are comprised of more than one > +architectural class and CPUs are comprised of cores of various efficiency > +and power capabilities. Power management strategies must be designed to = accommodate > +the complexities introduced by incorporating different core types. > +Heterogeneous systems can also extend to more than two architectural cla= sses as well. > +The purpose of the scheduling feedback mechanism is to provide informati= on to > +the operating system scheduler in real time such that the scheduler can = direct > +threads to the optimal core. > + > +``Classic cores`` are generally more performant and ``Dense cores`` are = generally more > +efficient. > +The goal of AMD's heterogeneous architecture is to attain power benefit = by sending > +background thread to the dense cores while sending high priority threads= to the classic > +cores. From a performance perspective, sending background threads to den= se cores can free > +up power headroom and allow the classic cores to optimally service deman= ding threads. > +Furthermore, the area optimized nature of the dense cores allows for an = increasing > +number of physical cores. This improved core density will have positive = multithreaded > +performance impact. > + > ... > + > +The mechanism used to trigger a table update like below events: > + * Thermal Stress Events > + * Silent Compute > + * Extreme Low Battery Scenarios What about below wording? ---- >8 ---- diff --git a/Documentation/arch/x86/amd-hfi.rst b/Documentation/arch/x86/am= d-hfi.rst index 351641ce28213c..5ada5c5b79f4b5 100644 --- a/Documentation/arch/x86/amd-hfi.rst +++ b/Documentation/arch/x86/amd-hfi.rst @@ -12,16 +12,15 @@ Overview -------- =20 AMD Heterogeneous Core implementations are comprised of more than one -architectural class and CPUs are comprised of cores of various efficiency -and power capabilities. Power management strategies must be designed to ac= commodate -the complexities introduced by incorporating different core types. -Heterogeneous systems can also extend to more than two architectural class= es as well. -The purpose of the scheduling feedback mechanism is to provide information= to -the operating system scheduler in real time such that the scheduler can di= rect -threads to the optimal core. +architectural class and CPUs are comprised of cores of various efficiency = and +power capabilities: performance-oriented *classic cores* and power-efficie= nt +*dense cores*. As such, power management strategies must be designed to +accommodate the complexities introduced by incorporating different core ty= pes. +Heterogeneous systems can also extend to more than two architectural class= es as +well. The purpose of the scheduling feedback mechanism is to provide +information to the operating system scheduler in real time such that the +scheduler can direct threads to the optimal core. =20 -``Classic cores`` are generally more performant and ``Dense cores`` are ge= nerally more -efficient. The goal of AMD's heterogeneous architecture is to attain power benefit by= sending background thread to the dense cores while sending high priority threads t= o the classic cores. From a performance perspective, sending background threads to dense= cores can free @@ -78,7 +77,8 @@ Power Management FW is responsible for detecting events t= hat would require a reordering of the performance and efficiency ranking. Table updates would happen relatively infrequently and occur on the time scale of seconds or m= ore. =20 -The mechanism used to trigger a table update like below events: +The following events trigger a table update: + * Thermal Stress Events * Silent Compute * Extreme Low Battery Scenarios > diff --git a/Documentation/arch/x86/index.rst b/Documentation/arch/x86/in= dex.rst > index 8ac64d7de4dc..7f47229f3104 100644 > --- a/Documentation/arch/x86/index.rst > +++ b/Documentation/arch/x86/index.rst > @@ -43,3 +43,4 @@ x86-specific Documentation > features > elf_auxvec > xstate > + amd_hfi Sphinx reports mismatched toctree entry name: Documentation/arch/x86/index.rst:7: WARNING: toctree contains reference to = nonexisting document 'arch/x86/amd_hfi' I have to fix it up: ---- >8 ---- diff --git a/Documentation/arch/x86/index.rst b/Documentation/arch/x86/inde= x.rst index 7f47229f3104e1..56f2923f52597c 100644 --- a/Documentation/arch/x86/index.rst +++ b/Documentation/arch/x86/index.rst @@ -43,4 +43,4 @@ x86-specific Documentation features elf_auxvec xstate - amd_hfi + amd-hfi Thanks. --=20 An old man doll... just what I always wanted! - Clara --ScYld6gsAtJ/5B+U Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQSSYQ6Cy7oyFNCHrUH2uYlJVVFOowUCZwnypAAKCRD2uYlJVVFO o6+GAQDrEa+eXvEryM52GrfrRsgFJemg9iRNdruOpF5csqRb7QD/dIlwwqoqSq3N aEclgc9riuX7haD/M3JqTJcey6S7qQ0= =LzcE -----END PGP SIGNATURE----- --ScYld6gsAtJ/5B+U--